Texas Instruments DM648 DSP Computer Hardware User Manual


  Open as PDF
of 47
 
www.ti.com
4DDR2MemoryControllerRegisters
DDR2MemoryControllerRegisters
Table17liststhememory-mappedregistersfortheDDR2memorycontroller.Seethedevice-specificdata
manualforthememoryaddressoftheseregisters.
Table17.DDR2MemoryControllerRegisters
OffsetAcronymRegisterDescriptionSection
00hMIDRModuleIDandRevisionRegisterSection4.1
04hDMCSTATDDR2MemoryControllerStatusRegisterSection4.2
08hSDCFGSDRAMConfigurationRegisterSection4.3
0ChSDRFCSDRAMRefreshControlRegisterSection4.4
10hSDTIM1SDRAMTiming1RegisterSection4.5
14hSDTIM2SDRAMTiming2RegisterSection4.6
20hBPRIOBurstPriorityRegisterSection4.7
E4hDMCCTLDDR2MemoryControllerControlRegisterSection4.8
36DSPDDR2MemoryControllerSPRUEK5A–October2007
SubmitDocumentationFeedback
 previous next