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DDR2 memory controller data bus
DDR_D[31:24]
(Byte Lane 3)
DDR_D[23:16]
(Byte Lane 2)
DDR_D[15:8]
(Byte Lane 1)
DDR_D[7:0]
(Byte Lane 0)
32-bit memory device
16-bit memory device
2.6AddressMapping
PeripheralArchitecture
Figure10showsthebytelanesusedontheDDR2memorycontroller.Theexternalmemoryisalways
rightalignedonthedatabus.
Figure10.ByteAlignment
TheDDR2memorycontrollerviewsexternalDDR2SDRAMasonecontinuousblockofmemory.This
statementistrueregardlessofthenumberofmemorydeviceslocatedonthechipselectspace.The
DDR2memorycontrollerreceivesDDR2memoryaccessrequestsalongwitha32-bitlogicaladdressfrom
therestofthesystem.Inturn,DDR2memorycontrollerusesthelogicaladdresstogeneratearow/page,
column,andbankaddressfortheDDR2SDRAM.Thenumberofcolumnandbankaddressbitsusedis
determinedbytheIBANKandPAGESIZEfields(seeTable5).TheDDR2memorycontrollerusesupto
14bitsfortherow/pageaddress.
Table5.BankConfigurationRegisterFieldsforAddressMapping
BitFieldBitValueBitDescription
IBANKDefinesthenumberofinternalbanksontheexternalDDR2memory.
01bank
1h2banks
2h4banks
3h8banks
PAGESIZEDefinesthepagesizeofeachpageoftheexternalDDR2memory.
0256words(requires8columnaddressbits)
1h512words(requires9columnaddressbits)
2h1024words(requires10columnaddressbits)
3h2048words(requires11columnaddressbits)
Figure11andFigure12showhowthelogicaladdressbitsmaptotherow,column,andbankbitsall
combinationsofIBANKandPAGESIZEvalues.Notethattheupperfourbitsofthelogicaladdresscannot
beusedformemoryaddressing,astheDDR2memorycontrollerhasamaximumaddressablememory
rangeof256Mbytes.
TheDDR2memorycontrolleraddresspinsprovidetherowandcolumnaddresstotheDDR2SDRAM,
thustheDDR2memorycontrollerappropriatelyshiftsthelogicaladdressduringrowandcolumnaddress
selection.ThebankaddressisdriventotheDDR2SDRAMusingthebankaddresspins.Thetwolower
bitsofthelogicaladdressdecodethevalueofthebyteenablepins(onlyusedforaccesseslessthanthe
widthoftheDDR2memorycontrollerdatabus).
Figure11.LogicalAddress-to-DDR2SDRAMAddressMapfor32-BitSDRAM
SPRUEK5A–October2007DSPDDR2MemoryController19
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