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2.11DDR2SDRAMMemoryInitialization
2.11.1DDR2SDRAMDeviceModeRegisterConfigurationValues
PeripheralArchitecture
DDR2SDRAMdevicescontainmodeandextendedmoderegistersthatconfigurethemodeofoperation
forthedevice.Theseregisterscontrolparameterssuchasbursttype,burstlength,andCASlatency.The
DDR2memorycontrollerprogramsthemodeandextendedmoderegistersoftheDDR2memoryby
issuingMRSandEMRScommandsduringtheinitializationsequencedescribedinSection2.11.2and
Section2.11.3.TheinitializationsequenceperformedbytheDDR2memorycontrolleriscompliantwith
theJESDEC79-2Aspecification.
TheDDR2memorycontrollerperformstheinitializationsequenceunderthefollowingconditions:
•Automaticallyfollowingahardorsoftreset,seeSection2.11.2.
•Followingawritetothetwoleast-significantbytesintheSDRAMconfigurationregister(SDCFG);see
Section2.11.3.
Attheendoftheinitializationsequence,theDDR2memorycontrollerperformsanauto-refreshcycle,
leavingtheDDR2memorycontrollerinanidlestatewithallbanksdeactivated.
Whentheinitializationsectionisstartedautomaticallyafterahardorsoftreset,commandsanddata
storedintheDDR2memorycontrollerFIFOsarelost.However,whentheinitializationsequenceis
initiatedbyawritetothetwoleast-significantbytesinSDCFG,dataandcommandsstoredintheDDR2
memorycontrollerFIFOsarenotlostandtheDDR2memorycontrollerensuresreadandwritecommands
arecompletedbeforestartingtheinitializationsequence.
TheDDR2memorycontrollerinitializesthemoderegisterandextendedmoderegister1ofthememory
devicewiththevaluesshownonTable9andTable10.TheDDR2SDRAMextendedmoderegisters2
and3areconfiguredwithavalueof0h.
Table9.DDR2SDRAMModeRegisterConfiguration
ModeModeRegister
RegisterBitFieldInitValueDescription
12Power-downMode0Activepower-downexittimebit.ConfiguredforFastexit.
11-9WriteRecoverySDTIM1.T_WRWriterecoverybitsforauto-precharge.Initializedusingthe
T_WRbitsoftheSDRAMtiming1register(SDTIM1).
8DLLReset0DLLresetbits.DLLisnotinreset.
7Mode0Operatingmodebit.Normaloperatingmodeisalways
selected.
6-4CASLatencySDCFG.CLCASlatencybits.InitializedusingtheCLbitsoftheSDRAM
configurationregister(SDCFG).
3BurstType0Bursttypebits.Sequentialburstmodeisalwaysused.
2-0BurstLength3hBustlengthbits.Aburstlengthof8isalwaysused.
Table10.DDR2SDRAMExtendedModeRegister1Configuration
ModeModeRegister
RegisterBitFieldInitValueDescription
12OutputBufferEnable0Outputbufferenablebits.Outputbufferisalwaysenabled.
11RDQSEnable0RDQSenablebits.Alwaysinitializedto0(RDQSsignals
disabled.)
10DQSenable0DQSenablebit.Alwaysinitializedto0(DQSsignals
enabled.)
9-7OCDOperation0hOff-chipdriverimpedancecalibrationbits.Thisbitisalways
initializedto0h.
6ODTValue(Rtt)0On-dieterminationeffectiveresistance(Rtt)bit.Together
withbit2,thisbitselectsthevalueforRttas75Ω.
5-3AdditiveLatency0hAdditivelatencybits.Alwaysinitializedto0h(noadditive
latency).
SPRUEK5A–October2007DSPDDR2MemoryController27
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