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Bits in the Operation Status Group Event register which are set can be
determined with the command:
STATus:OPERation:EVENt?
This command returns the decimal weighted sum of the set bit(s).
Clearing the Operation
Event Register Bits
Bits in the Operation Status Group Event register are cleared with the
command:
STATus:OPERation:EVENt?
or the bits can be cleared with the command:
*CLS
The Operation Status Group Enable register is cleared (all bits masked) by
sending the command:
STATus:OPERation:ENABle 0
Using the Operation
Status Group Registers
The following example shows the sequence of commands used to setup and
respond to an interrupt using the system instrument interrupt servicing routine.
NOTE An interrupt handler must be assigned to handle the interrupt on the VXIbus
backplane interrupt line specified. See "Interrupt Line Allocation" in Chapter 2
for more information.
!Call computer subprogram Intr_resp when a service request
! is received due to an interrupt on a VXIbus backplane
! interrupt line.
ON INTR 7 CALL Intr_resp
ENABLE INTR 7;2
!Unmask bit 7 in the Status Byte register so that a service
! request (SRQ) will occur when an interrupt occurs.
!Unmask bit 8 in the Operation Status Group Enable register
!so that when the interrupt occurs it will set bit 7 in the
!Status Byte register.
OUTPUT 70900; "*SRE 128"
OUTPUT 70900; "STAT:OPER:ENAB 256"
!Set up interrupt line 5 and enable interrupt response data
!to be generated.
OUTPUT 70900; "DIAG:INT:SETUP5 ON"
OUTPUT 70900; "DIAG:INT:ACT ON"
.
. (Program which executes until interrupt occurs)
.
!Computer service request routine which does an SPOLL
!to determine the cause of the interrupt, then reads
!(and clears) the Operation Event register to determine which
!event occurred, and then reads the interrupt acknowledge
! response (which also clears condition register bit 8).
Controlling Instruments Using GPIB 6-9