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Technical Reference Guide
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition - September 1997
5-19
FIFO Control Register, I/O Port 3FAh/2FAh (Write Only)
This write-only register enables and clears the FIFOs and set the trigger level and DMA mode.
Bit Function
7,6 Receiver Trigger Level
00 = 1 byte 10 = 8 bytes
01 = 4 bytes 11 = 14 bytes
5..3 Reserved
2 Transmit FIFO Reset (if set)
1 Receive FIFO Reset (if set)
0 FIFOs Enable/Disable
0 = Disable TX/RX FIFOs, 1 = Enable TX/RX FIFOs
Line Control Register, I/O Port 3FBh/2FBh
This register specifies the data transmission format.
Bit Function
7 RX Buffer / TX Holding Reg. And Divisor Rate Reg. Access
0 = RX buffer, TX holding reg., and Interrupt En. Reg. Are accessable.
1 = Divisor Latch reg. is accessable.
6 Break Control (forces SOUT signal low if set)
5 Stick Parity. If set, even parity bit is logic 0, odd parity bit is logic 1
4 Parity Type
0 = Odd, 1 = Even
3 Parity Enable:
0 = Disabled, 1 = Enabled
2 Stop Bit:
0 = 1 stop bit, 1 = 2 stop bits
1,0 Word Size:
00 = 5 bits 10 = 7 bits
01 = 6 bits 11 = 8 bits
Modem Control Register, I/O Port 3FCh/2FCh
This register controls the modem signal lines
Bit Function
7..5 Reserved
4 Internal Loopback Enabled (if set)
3 Serial Interface Interrupts Enabled (if set)
2 Reserved
1 RTS Signal Active (if set)
0 DTR Signal Active (if set)