Compaq 4000S Personal Computer User Manual


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Technical Reference Guide
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
ix
LIST OF TABLES
T
ABLE
1–1. A
CRONYMS AND
A
BBREVIATIONS
.......................................................................................1-3
T
ABLE
2–1. A
RCHITECTURAL
C
OMPARISON
.............................................................................................2-8
T
ABLE
2–2. S
UPPORT
C
HIPSETS
.......................................................................................................... 2-11
T
ABLE
2–3. G
RAPHICS
S
UBSYSTEM
O
VERVIEW
.................................................................................... 2-12
T
ABLE
2–4. E
NVIRONMENTAL
S
PECIFICATIONS
.................................................................................... 2-13
T
ABLE
2–5. E
LECTRICAL
S
PECIFICATIONS
........................................................................................... 2-13
T
ABLE
2–6. P
HYSICAL
S
PECIFICATIONS
............................................................................................... 2-13
T
ABLE
2–7. D
ISKETTE
D
RIVE
S
PECIFICATIONS
..................................................................................... 2-14
T
ABLE
2–8. 8
X
CD-ROM D
RIVE
S
PECIFICATIONS
................................................................................ 2-14
T
ABLE
2–9. H
ARD
D
RIVE
S
PECIFICATIONS
........................................................................................... 2-15
T
ABLE
3–1. P
ROCESSOR
/M
EMORY
A
RCHITECTURAL
H
IGHLIGHTS
............................................................3-1
T
ABLE
3–2. P
ENTIUM
MMX M
ICROPROCESSOR
B
US
/C
ORE
S
PEED
S
WITCH
S
ETTINGS
.............................3-4
T
ABLE
3–3. SW1 B
US
/C
ORE
S
PEED
P
OSITIONS TO
GPIO A
SSIGNMENTS
...................................................3-4
T
ABLE
3–4. SDRAM P
ERFORMANCE
T
IMES
............................................................................................3-5
T
ABLE
3–5. SPD A
DDRESS
M
AP
(SDRAM DIMM)................................................................................. 3-6
T
ABLE
3–6. H
OST
/PCI B
RIDGE
C
ONFIGURATION
R
EGISTERS
(VT82C595) .............................................. 3-8
T
ABLE
4–1. 32-B
IT
PCI B
US
C
ONNECTOR
P
INOUT
.................................................................................4-3
T
ABLE
4–2. PCI B
US
M
ASTERING
D
EVICES
...........................................................................................4-4
T
ABLE
4–3. PCI D
EVICE
C
ONFIGURATION
A
CCESS
................................................................................4-6
T
ABLE
4–4. PCI F
UNCTION
C
ONFIGURATION
A
CCES
..............................................................................4-7
T
ABLE
4–5. PCI D
EVICE
I
DENTIFICATION
.............................................................................................4-8
T
ABLE
4–6. PCI/ISA B
RIDGE
C
ONFIGURATION
R
EGISTERS FOR THE
VT82C586 (P55C-B
ASED
S
YSTEMS
)4-10
T
ABLE
4–7. ISA E
XPANSION
C
ONNECTOR
P
INOUT
............................................................................... 4-12
T
ABLE
4–8. D
EFAULT
DMA C
HANNEL
A
SSIGNMENTS
......................................................................... 4-15
T
ABLE
4–9. DMA P
AGE
R
EGISTER
A
DDRESSES
................................................................................... 4-16
T
ABLE
4–10. DMA C
ONTROLLER
R
EGISTERS
...................................................................................... 4-17
T
ABLE
4–11. M
ASKABLE
I
NTERRUPT
P
RIORITIES AND
A
SSIGNMENTS
.................................................... 4-19
T
ABLE
4–12. M
ASKABLE
I
NTERRUPT
C
ONTROL
R
EGISTERS
.................................................................. 4-19
T
ABLE
4–13. I
NTERVAL
T
IMER
F
UNCTIONS
......................................................................................... 4-22
T
ABLE
4–14. I
NTERVAL
T
IMER
C
ONTROL
R
EGISTERS
........................................................................... 4-22
T
ABLE
4–15. C
LOCK
G
ENERATION AND
D
ISTRIBUTION
(P
ENTIUM
-B
ASED
S
YSTEM
)............................... 4-23
T
ABLE
4–16. C
ONFIGURATION
M
EMORY
(CMOS) M
AP
....................................................................... 4-25
T
ABLE
4–17. S
YSTEM
I/O M
AP
........................................................................................................... 4-41
T
ABLE
4–18. 87307 I/O C
ONTROLLER
P
N
P S
TANDARD
C
ONTROL
R
EGISTERS
........................................ 4-42
T
ABLE
4–19. S
YSTEM
M
ANAGEMENT
C
ONTROL
R
EGISTERS
................................................................... 4-44
T
ABLE
5–1. IDE PCI C
ONFIGURATION
R
EGISTERS
................................................................................5-2
T
ABLE
5–2. IDE B
US
M
ASTER
C
ONTROL
R
EGISTERS
.............................................................................5-2
T
ABLE
5–3. IDE ATA C
ONTROL
R
EGISTERS
.........................................................................................5-3
T
ABLE
5–4. IDE C
ONTROLLER
C
OMMANDS
..........................................................................................5-6
T
ABLE
5–5. 40-P
IN
IDE C
ONNECTOR
P
INOUT
.......................................................................................5-8
T
ABLE
5–6. 40-P
IN
IDE C
ONNECTOR
P
INOUT
.......................................................................................5-9
T
ABLE
5–7. D
ISKETTE
D
RIVE
C
ONTROLLER
C
ONFIGURATION
R
EGISTERS
............................................. 5-11
T
ABLE
5–8. D
ISKETTE
D
RIVE
C
ONTROLLER
R
EGISTERS
....................................................................... 5-12
T
ABLE
5–9. 34-P
IN
D
ISKETTE
D
RIVE
C
ONNECTOR
P
INOUT
................................................................... 5-14
T
ABLE
5–10. DB-9 S
ERIAL
C
ONNECTOR
P
INOUT
................................................................................. 5-15
T
ABLE
5–11. S
ERIAL
I
NTERFACE
C
ONFIGURATION
R
EGISTERS
.............................................................. 5-16
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