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MVME3100 Single Board Computer Installation and Use (6806800M28C)
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6.1.10 Interrupt Detect Register
The MVME3100 provides an Interrupt Detect register that may be read by the system software
to determine which of the Ethernet PHYs originated their combined (OR'd) interrupt.
TSEC1_PHY: TSEC1 PHY interrupt. If cleared, the TSEC1 interrupt is not asserted. If set, the
TSEC1 interrupt is asserted.
TSEC2_PHY: TSEC2 PHY interrupt. If cleared, the TSEC2 interrupt is not asserted. If set, the
TSEC2 interrupt is asserted.
FEC_PHY: FEC PHY interrupt. If cleared, the FEC interrupt is not asserted. If set, the FEC
interrupt is asserted.
RSVD: Reserved for future implementation.
6.1.11 Presence Detect Register
The MVME3100 provides a Presence Detect register that may be read by the system software
to determine the presence of optional devices.
Table 6-11 Interrupt Detect Register
REG Interrupt Detect Register - 0xE2000007
BIT 76543210
FIELD
RSVD
RSVD
RSVD
RSVD
RSVD
FEC_PHY
TSEC2_PHY
TSEC1_PHY
OPERRRRRRRRR
RESET11100000
Table 6-12 Presence Detect Register
REG Presence Detect Register - 0xE2000008
BIT 76543210