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Service Manual
2A-38
2A-71. Main PCA Connector
The Memory Card Interface PCA interfaces to the Main PCA through a 40-pin, right
angle connector (A6P2). This connector routes eight bits of the Microprocessor data bus,
the lower four bits of the address bus, memory control, interrupt and address decode
signals from the Main PCA to the Memory Card Interface PCA. The Memory Card
Interface PCA is powered by the +5.0V dc power supply (VCC). The pinout of the high
density ribbon cable that connects the Main PCA to the Memory Card Interface PCAis
carefully selected to prevent cross-talk between signals and to provide low impedance
connections to the VCC power supply.
2A-72. Microprocessor Interface
The timing of Microprocessor read and write accesses to the Memory Card Controller
(A6U1) are controlled internally by the Memory Card Controller which determines
whether wait states are required when the Microprocessor accesses one of its internal
registers.
When a register in the Memory Card Controller (A6U1) is read, the four address bits
select one of the internal registers to read and then the XMCARD* signal (A6U1-49) is
driven to a low level by the Microprocessor. The XRDU* signal (A6U1-50) is then
driven low by A1U11-14 to enable the data outputs from the Memory Card Controller
(D8 through D15). At the end of the read access, both XMCARD* and XRDU* are
driven high again.
When a register in the Memory Card Controller (A6U1) is written, the four address bits
select one of the internal registers to write and then the XMCARD* signal (A6U1-49) is
driven to a low level by the Microprocessor. The XWRU* signal (A6U1-51) is then
driven low by A1U11-13 to initiatethe transfer of the data bus inputs on the Memory
Card Controller (D8 through D15) to the internal register. At the end of the write access,
both XMCARD* and XRDU* are driven high again and the data is latched into the
internal register.
If no wait states are required, the DTACK* signal (A6U1-58) will be driven low after the
next low to high transition of the system clock (A6U1-30) to indicate to the
Microprocessor that the data transfer has been acknowledged and the read or write
access may be completed. The DTACK* signal is a tri-state bus that is pulled up to VCC
by resistor A1R83 and pulled low by devices being accessed by the Microprocessor.
If wait states are required, the DTACK* signal (A6U1-58)will not go low until the
proper number of wait states have been inserted.The Memory Card Controller counts
cycles of the system clock (A6U1-30) and when the correct number of wait states have
been done, the DTACK* signal will go low.
Accesses to internal registers should be done with no wait states, and accesses through
the Memory Card Controller to the Memory Card automatically add two wait states.
2A-73. Memory Card Controller
The Memory Card Controller (A6U1) is a Field Programmable Gate Array (FPGA) that
automatically loads its configuration upon power-up from a serial memory device
(A6U3).While it is configuring, the FPGA holds the memory CE input (A6U3-4) low
and toggles the CLK input (A6U3-2) to serially shift the configuration data out of the
memory on the D output (A6U3-1) and into the FPGA.When configuration is complete,
the FPGA should release the CE input(A6U3-4) allowing it to be pulled high by resistor
A6R8.