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Chapter 4 System Support
4.2 PCI BUS OVERVIEW
NOTE: This section describes the PCI bus in general and highlights bus
implementation in this particular system. For detailed information regarding PCI bus
operation, refer to the PCI Local Bus Specification Revision 2.2.
These systems implement a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2)
operating at 33 MHz. The PCI bus handles address/data transfers through the identification of
devices and functions on the bus. A device is typically defined as a component or slot that resides
on the PCI bus (although some components such as the IGP and MCP or MCP-2 are organized as
multiple devices). A function is defined as the end source or target of the bus transaction. A
device may contain one or more functions.
In the standard configuration these systems use a hierarchy of three PCI buses (Figure 4-1). The
PCI bus #0 is internal to the chipset components and is not physically accessible. The AGP bus
that services the AGP slot is designated as PCI bus #1. All PCI slots reside on PCI bus #2.
Network
Interface
Function
USB
Cntlr. b
Function
PCI
Bus #2
PCI Connector 1
PCI Connector 2
PCI Connector 3
PCI Bus #0
AC97
Audio
Function
Legacy
Function
SMBus
Controller
Function
USB
Cntlr. A
Function
IDE
Controller
Function
PCI Bridge
Function
HT Link I/F
MCP or MCP-2 Component
Hyper Transfer Link Bus
Mem. Cntlr.
Function
PCI
Bus #0
HT Link I/F
Integrated
Graphics
Controller
AGP
Bridge
Function
IGP Component
PCI Bus #1
(AGP Bus)
AGP Connector
NOTE:
Not implemented in the D315 system.
Figure 4-1. PCI Bus Devices and Functions
Compaq D315 and hp d325 Personal Computers
Featuring the AMD Athlon XP Processor
Second Edition – April 2003
4-2