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Chapter 5 Input/Output Interfaces
5.6 KEYBOARD/POINTING DEVICE INTERFACE
The keyboard/pointing device interface function is provided by the LPC47B367 I/O controller
component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as
simply the “8042”) to communicate with the keyboard and pointing device using bi-directional
serial data transfers. The 8042 handles scan code translation and password lock protection for the
keyboard as well as communications with the pointing device. This section describes the interface
itself. The keyboard is discussed in the Appendix C.
5.6.1 KEYBOARD INTERFACE OPERATION
The data/clock link between the 8042 and the keyboard is uni-directional for Keyboard Mode 1
and bi-directional for Keyboard Modes 2 and 3. (These modes are discussed in detail in Appendix
C). This section describes Mode 2 (the default) mode of operation.
Communication between the keyboard and the 8042 consists of commands (originated by either
the keyboard or the 8042) and scan codes from the keyboard. A command can request an action or
indicate status. The keyboard interface uses IRQ1 to get the attention of the CPU.
The 8042 can send a command to the keyboard at any time. When the 8042 wants to send a
command, the 8042 clamps the clock signal from the keyboard for a minimum of 60 us. If the
keyboard is transmitting data at that time, the transmission is allowed to finish. When the 8042 is
ready to transmit to the keyboard, the 8042 pulls the data line low, causing the keyboard to
respond by pulling the clock line low as well, allowing the start bit to be clocked out of the 8042.
The data is then transferred serially, LSb first, to the keyboard (Figure 5-5). An odd parity bit is
sent following the eighth data bit. After the parity bit is received, the keyboard pulls the data line
low and clocks this condition to the 8042. When the keyboard receives the stop bit, the clock line
is pulled low to inhibit the keyboard and allow it to process the data.
D1
D2
D3
D4
D5
D6
Parity
Start
Bit
0
D0
(LSb)
1
D7
(MSb)
1
Stop
Bit
0
0
1
1
0
1
1
1
Parameter
Minimum
Maximum
Tsh
Tss
Tcy
Tch
Tcl
Th
Data
Clock
Tcy (Cycle Time) 0 µs 80 µs
Tcl (Clock Low) 25 µs 35 µs
Tch (Clock High) 25 µs 45 µs
Th (Data Hold) 0 µs 25 µs
Tss (Stop Bit Setup) 8 µs 20 µs
Tsh (Stop Bit Hold) 15 µs 25 µs
Figure 5-5. 8042-To-Keyboard Transmission of Code EDh, Timing Diagram
5-16 Compaq D315 and hp d325 Personal Computers
Featuring the AMD Athlon XP Processor
Second Edition – April 2003