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Technical Reference Guide
CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM.............................................................................
3.1 INTRODUCTION....................................................................................................................... 3-1
3.2 ATHLON
XP
PROCESSOR....................................................................................................... 3-2
3.2.1 PROCESSOR OVERVIEW................................................................................................ 3-2
3.2.2 PROCESSOR UPGRADING.............................................................................................. 3-4
3.3
MEMORY
SUBSYSTEM........................................................................................................... 3-5
CHAPTER 4 SYSTEM SUPPORT ..............................................................................................................
4.1 INTRODUCTION....................................................................................................................... 4-1
4.2 PCI
BUS
OVERVIEW................................................................................................................ 4-2
4.2.1
PCI BUS TRANSACTIONS............................................................................................... 4-3
4.2.2 PCI BUS MASTER ARBITRATION................................................................................. 4-6
4.2.3 OPTION ROM MAPPING ................................................................................................. 4-7
4.2.4 PCI INTERRUPTS.............................................................................................................. 4-7
4.2.5 PCI POWER MANAGEMENT SUPPORT........................................................................ 4-7
4.2.6 PCI SUB-BUSSES.............................................................................................................. 4-7
4.2.7 PCI CONNECTOR ............................................................................................................. 4-8
4.3 AGP
BUS
OVERVIEW .............................................................................................................. 4-9
4.3.1 BUS TRANSACTIONS...................................................................................................... 4-9
4.3.2 AGP CONNECTOR.......................................................................................................... 4-13
4.4 SYSTEM
RESOURCES ........................................................................................................... 4-14
4.4.1 INTERRUPTS................................................................................................................... 4-14
4.4.2 DIRECT MEMORY ACCESS.......................................................................................... 4-18
4.5 SYSTEM
CLOCK
DISTRIBUTION ........................................................................................ 4-21
4.6 REAL-TIME
CLOCK
AND
CONFIGURATION
MEMORY.................................................. 4-22
4.6.1 CLEARING CMOS........................................................................................................... 4-22
4.6.2 CMOS ARCHIVE AND RESTORE................................................................................. 4-23
4.6.3 STANDARD CMOS LOCATIONS ................................................................................. 4-23
4.7 SYSTEM
MANAGEMENT...................................................................................................... 4-24
4.7.1 SECURITY FUNCTIONS................................................................................................ 4-24
4.7.2 POWER MANAGEMENT ............................................................................................... 4-26
4.7.3 SYSTEM STATUS ........................................................................................................... 4-26
4.7.4 THERMAL SENSING AND COOLING ......................................................................... 4-27
4.8 REGISTER
MAP
AND
MISCELLANEOUS
FUNCTIONS.................................................... 4-30
4.8.1 SYSTEM I/O MAP ........................................................................................................... 4-30
4.8.2 LPC47B367 I/O CONTROLLER FUNCTIONS.............................................................. 4-31
Compaq D315 and hp d325 Personal Computers
Featuring the AMD Athlon XP Processor
Second Edition –- April 2003
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