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Chapter 4 System Support
AGP 8X Transfers
The AGP 8X transfer rate (supported on d325 models only) allows 32 bytes of data to be
transferred in one clock cycle. As with the other transfer rates the 66-MHz CLK signal is used
only for qualifying control signals while strobe signals are used to latch each 4-byte transfer on
the AD lines. As shown in Figure 4-8, 4-byte block DnA is latched by the falling edge of
AD_STBx while DnB is latched by the falling edge of AD_STBx-. The signal level for AGP 8X
transfers can be 0.8 or 1.5 VDC.
Figure 4-8. AGP 8X Data Transfer (Peak Transfer Rate: 2128 MB/s)
D1A D2A D1B D3A D3B D4A D4B D2B
TRDY
AD_STBF
CLK
AD
AD_STBS
T2
T1
1
Data
Latched
s
t
Final Data
Latched
Compaq D315 and hp d325 Personal Computers
Featuring the AMD Athlon XP Processor
Second Edition – April 2003
4-12