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10-10 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
External Bus
A simpler but lower performance method would be to assert Hold to the Intel
®
80200 processor,
wait for all outstanding transactions to complete, grant the issue bus to the alternate master (using
the issue bus pins with the Intel
®
80200 processor bus protocols, or whatever protocol the alternate
master required) and give the bus back to the Intel
®
80200 processor only once the alternate bus
master is completely finished.
The Lock signal is active in transactions which require atomicity on a read/write pair. The
minimum level of memory granularity over which a lock can be held should be at least 32 bytes.
That is: if a master on the bus asserts Lock on a particular address, the naturally aligned 32-byte
block that contains that address should be considered protected from access by other bus masters. It
is permissible, of course, to consider all of memory locked and to hold off all accesses by other bus
masters.
The interaction of Hold with the Lock signal is interesting. If the Lock pin is asserted by the Intel
®
80200 processor, the Intel
®
80200 processor is executing an ARM* Swap instruction, which does a
read from a memory location followed atomically by a write to the same location. This is used for
updating semaphores in shared memory. Until a request appears that does not have the Lock signal
asserted, the chipset should not allow accesses of any kind to the memory location of the read that
asserted the lock.
It is possible that the chipset may assert Hold to allow another master on the bus on clock edge n
and the Intel
®
80200 processor issues a read request and asserts Lock on the same clock edge n. In
this case, the chipset should not let another master access memory at this time -- the Intel
®
80200
processor is stalled waiting for access to the bus. However, the Intel
®
80200 processor continues to
respect the Hold pin and floats the request bus as it normally would. This allows the chipset to have
a guaranteed delay between Hold assertion and the Intel
®
80200 processor floating the pins.
In the general case, the Hold pin should be deasserted a cycle or two later (speed here is not
critical, as long as no other master is allowed to initiate a memory request) and the Intel
®
80200
processor continues on with the atomic pair of requests. Once the write request that deasserts Lock
is issued, the chipset can reassert Hold and give the bus to another master.
If the system designer knows that the other requesting master is not accessing the same 32-byte
memory region as the locked read, the chipset may choose to not deassert Hold, and can continue
on with the multimaster request.
Another possibility is for the chipset to accept the read with Lock request and store it into the
chipset queues, but to delay execution of the read with Lock until after the transactions from the
other bus master to avoid a semaphore conflict.
Any of these strategies work as long as there are no accesses to the 32-byte memory region of the
locked read after the read has executed and before the next write request is executed (which
deasserts Lock).