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Developer’s Manual March, 2003 4-9
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Instruction Cache
Software can lock down several different routines located at different memory locations. This may
cause some sets to have more locked lines than others as shown in Figure 4-2.
Example 4-4 on page 4-9 shows how a routine, called “lockMe” in this example, might be locked
into the instruction cache. Note that it is possible to receive an exception while locking code (see
Section 2.3.4, “Event Architecture” on page 2-12).
4.3.5 Unlocking Instructions in the Instruction Cache
The Intel
®
80200 processor provides a global unlock command for the instruction cache. Writing
to coprocessor 15, register 9 unlocks all the locked lines in the instruction cache and leaves them
valid. These lines then become available for the round-robin replacement algorithm. (See
Table 7-14, “Cache Lockdown Functions” on page 7-14 for the exact command.)
Example 4-4. Locking Code into the Cache
lockMe: ; This is the code that will be locked into the cache
mov r0, #5
add r5, r1, r2
. . .
lockMeEnd:
. . .
codeLock: ; here is the code to lock the “lockMe” routine
ldr r0, =(lockMe AND NOT 31); r0 gets a pointer to the first line we
should lock
ldr r1, =(lockMeEnd AND NOT 31); r1 contains a pointer to the last line we
should lock
lockLoop:
mcr p15, 0, r0, c9, c1, 0; lock next line of code into ICache
cmp r0, r1 ; are we done yet?
add r0, r0, #32 ; advance pointer to next line
bne lockLoop ; if not done, do the next line