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3-2 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Memory Management
3.2 Architecture Model
3.2.1 Version 4 vs. Version 5
ARM* MMU Version 5 Architecture introduces the support of tiny pages, which are 1 KByte in
size. The reserved field in the first-level descriptor (encoding 0b11) is used as the fine page table
base address. The exact bit fields and the format of the first and second-level descriptors can be
found in Section 2.3.2, “New Page Attributes” on page 2-9.
3.2.2 Memory Attributes
The attributes associated with a particular region of memory are configured in the memory
management page table and control the behavior of accesses to the instruction cache, data cache,
mini-data cache and the write buffer. These attributes are ignored when the MMU is disabled.
To allow compatibility with older system software, the new Intel
®
80200 processor attributes take
advantage of encoding space in the descriptors that was formerly reserved.
3.2.2.1 Page (P) Attribute Bit
The P bit specifies that the associated memory should be protected with ECC. The P bit is only
present in the first level descriptors. Thus, ECC memory is specified with a 1 megabyte granularity.
If the MMU is disabled, ECC is disabled for all memory accesses. If the MMU is enabled, ECC is
enabled for a region of memory if:
• its P bit in the first level descriptor for that virtual memory is set and
• the BCU has ECC enabled (see Chapter 11, “Bus Controller”)
Accesses to memory for page walks do not use the MMU. For these accesses, ECC is enabled if:
• the CP15 Auxiliary Control Register enables it (see Section 7.2.2, “Register 1: Control and
Auxiliary Control Registers” on page 7-7) and
• the BCU has ECC enabled (see Chapter 11, “Bus Controller”)
3.2.2.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits
3.2.2.3 Instruction Cache
When examining these bits in a descriptor, the Instruction Cache only utilizes the C bit. If the C bit
is clear, the Instruction Cache considers a code fetch from that memory to be non-cacheable, and
does not fill a cache entry. If the C bit is set, then fetches from the associated memory region are
cached.