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Developer’s Manual March, 2003 B-1
Optimization Guide B
B.1 Introduction
This appendix contains optimization techniques for achieving the highest performance from the
Intel
®
80200 processor based on Intel
®
XScale
™
microarchitecture (compliant with the ARM*
Architecture V5TE). It is written for developers who are optimizing compilers or performance
analysis tools for the Intel
®
80200 processor based processors. It can also be used by application
developers to obtain the best performance from their assembly language code. The optimizations
presented in this chapter are based on the Intel
®
80200 processor core, and hence can be applied to
all products that are based on the Intel
®
80200 processor core.
The Intel
®
80200 processor architecture includes a superpipelined RISC architecture with an
enhanced memory pipeline. The Intel
®
80200 processor instruction set is based on ARM* V5TE
architecture; however, the Intel
®
80200 processor includes additional instructions. Code generated
for the SA-110, SA-1100 and SA-1110 execute on the Intel
®
80200 processors, however to obtain
the maximum performance of your application code, it should be optimized for the Intel
®
80200
processor architecture using the techniques presented in this document.
B.1.1 About This Guide
This guide assumes that you are familiar with the Intel
®
StrongARM* instruction set and the C
language. It consists of the following sections:
Section B.1, “Introduction”. Outlines the contents of this guide.
Section B.2, “Intel
®
80200 Processor Pipeline”. This chapter provides an overview of the Intel
®
80200 processor pipeline behavior.
Section B.3, “Basic Optimizations”. This chapter outlines basic Intel
®
StrongARM* optimizations
that can be applied to the Intel
®
80200 processors.
Section B.4, “Cache and Prefetch Optimizations”. This chapter contains optimizations for efficient
use of caches. Also included are optimizations that take advantage of the prefetch instruction of the
Intel
®
80200 processor.
Section B.5, “Instruction Scheduling”. This chapter shows how to optimally schedule code for the
Intel
®
80200 processor pipeline.
Section B.6, “Optimizing C Libraries”. This chapter contains information relating to optimizations
for C library routines.
Section B.7, “Optimizations for Size”. This chapter contains optimizations that reduce the size of
the generated code. Thumb* optimizations are also included.