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Developer’s Manual March, 2003 2-9
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Programming Model
2.3.2 New Page Attributes
The Intel
®
80200 processor extends the page attributes defined by the C and B bits in the page
descriptors with an additional X bit. This bit allows four more attributes to be encoded when X=1.
These new encodings include allocating data for the mini-data cache and write-allocate caching. A
full description of the encodings can be found in Section 3.2.2, “Memory Attributes” on page 3-2.
The Intel
®
80200 processor retains ARM definitions of the C and B encoding when X = 0, which is
different than the first generation Intel
®
StrongARM* products. The memory attribute for the
mini-data cache has been moved and replaced with the write-through caching attribute.
When write-allocate is enabled, a store operation that misses the data cache (cacheable data only)
generates a line fill. If disabled, a line fill only occurs when a load operation misses the data cache
(cacheable data only).
Write-through caching causes all store operations to be written to memory, whether they are
cacheable or not cacheable. This feature is useful for maintaining data cache coherency.
The Intel
®
80200 processor also added a P bit in the first level descriptors to identify which pages
of memory are protected with ECC.
A descriptor with the P bit set indicates the corresponding page in memory is ECC protected. If the
BCUs ECC mode is enabled (see Chapter 11, “Bus Controller”) then writes to such a page are
accompanied with an ECC and reads are validated by an ECC.
Bit 1 in the Control Register (coprocessor 15, register 1, opcode=1) enables ECC protection for
memory accesses made during page table walks.
These attributes are programmed in the translation table descriptors, which are highlighted in
Table 2-8, “First-level Descriptors” on page 2-10, Table 2-9, “Second-level Descriptors for Coarse
Page Table” on page 2-10 and Table 2-10, “Second-level Descriptors for Fine Page Table” on
page 2-10. Two second-level descriptor formats have been defined for Intel
®
80200 processor, one
is used for the coarse page table and the other is used for the fine page table.