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ATM2 OC12/STM4 IQ PIC
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JUNOS 6.1 and laterSoftware release
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One OC12 port
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Power requirement: 0.41 A @ 48 V (20 W)
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Intelligent queuing (IQ) PICs support fine-grained queuing per logical interface
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Conforms to ANSI T1.105-1991 and T1E1.2/93-020R1
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Complies with ATM and SONET/SDH standards
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Alarm and event counting and detection
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Compatible with well-known ATM switches
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ATM switch ID, which displays the switch IP address and local interface name of the
adjacent Fore ATM switches
Description
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One 3010 SAR for segmentation and reassembly into 53-byte ATM cells
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High-performance parsing of SONET/SDH frames
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ASIC-based packet segmentation and reassembly (SAR) management and output port
queuing
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64 MB SDRAM memory for ATM SAR
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Packet buffering, Layer 2 parsing
Hardware features
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Circuit cross-connect for leveraging ATM access networks
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User-configurable virtual circuit (VC) and virtual path (VP) support
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Support for idle cell or unassigned cell transmission
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OAM fault management processes alarm indication signal (AIS), remote defect indication
(RDI), and loop cells
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Point-to-point and point-to-multipoint mode Layer 2 counters per VC and per VP
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Local and remote loopback
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ATM Inverse ARP, which enables routers to automatically learn the IP address of the
router on the far end of an ATM PVC
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Simple Network Management Protocol (SNMP):
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Management Information Base (MIB) 2 (RFC 1213)
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ATM MIB (RFC 1695)
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SONET MIB
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Unspecified bit rate (UBR), non-real-time variable bit rate (VBR), and constant bit rate
(CBR) traffic shaping
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Per-VC or per-VP traffic shaping
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Support for F4 OAM cells
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Support for 16-bit VCI range
Software features
16 ■ ATM2 OC12/STM4 IQ PIC
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