Filter
Top Products
KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 10 of 120 Ver. 0.9 KS152JB2
Writing to a Port
During the execution of an instruction that changes the value of a port SFR, the new value arrives
at the port latch during S6P2. However, the port latch contents do not appear on the port pins till
the next P1 phase. Therefore the new port data will appear on the port pins at S1P1 of the next
machine cycle.
Read-Modify-Write Feature
Each port is split into its SFR and its corresponding I/O pad. Therefore there are two options
available for a port read access. Either the SFR latch contents can be read or the input from the I/
O pads can be read. The instructions that read the latch, modify the value and write it back to the
latch are called “read-modify-write” instruction. In such instructions the latch and not the pin is
read. The instruction of this category are listed as follows
ANL logical AND
ORL logical OR
XRL logical XOR
JBC jump if bit = 1 and then clear bit
CPL complement bit
INC increment
DEC decrement
DJNZ decrement and jump if not zero
MOV PX.Y, C move carry bit to bit Y of Port X
CLR PX.Y clear bit Y of port X
SETB PX.Y set bit Y of X
2.5 Ports 4,5 and 6
Ports 4,5 and 6 operation is identical to Ports 1-3 on the 80C51. Ports 5 and 6 exist only on the
“JB” and “JD” version of the C152 and can either function as standard I/O ports or can be config-
ured so that program memory fetches are performed with these two ports. To configure ports 5
and 6 as standard I/O ports, EBEN is tied to a logic low. When in this configuration, ports 5 and 6
operation is identical to that of port 4 except they are not bit addressable. To configure ports 5 and
6 to fetch program memory, EBEN is tied to a logic high. When using ports 5 and 6 to fetch the
program memory, the signal EPSEN is used to enable the external memory device instead of
PSEN. Regardless of which ports are used to fetch program memory, all data memory fetches
occur over ports 0 and 2. The 80C152JB and 80C152JD are available as ROMless devices only.
ALE is still used to latch the address in all configurations. Table 2.1 summarizes the control sig-
nals and how the ports may be used.