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Chapter 3 Hardware Overview
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National Instruments Corporation 3-13 PCI-4451/4452 User Manual
Device Configuration Issues
Selecting a sample rate that is less than two times the frequency of a band
of interest can lead you to believe the board is functioning improperly. By
undersampling the signal, you could receive what appears to be a DC
signal. This situation is due to the sharp antialiasing filters that remove
frequency components above the sampling frequency. If you have a
situation where this occurred, simply increase the sample rate until it meets
the requirements of the Shannon Sampling Theorem. For more information
on the filters and aliasing, refer to Chapter 6, Theory of Analog Operation.
Unlike other converter technologies, delta-sigma converters must be run
continuously and at a minimum clock rate. To operate within guaranteed
specifications, the A/D converters should operate at a minimum sample rate
of 5.0 kS/s and the D/A converters should operate at a minimum update rate
of 1.25 kS/s. This minimum rate is required to keep the internal circuitry of
the converters running within specifications. You are responsible for
selecting sample and update rates that fall within the specified limits.
Failure to do so could greatly affect the specifications.
User.book Page 13 Tuesday, April 14, 1998 10:20 AM