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Programming the GPIB-COM Section Five
GPIB-COM User Manual 5-12 © National Instruments Corporation
Line Status Register
Offset from Base I/O Address = 5
Register Address = XFD
7 654 321
0
TEMT THRE
0
BI
FE
PE OE DR
R
The Line Status Register provides information about the status of the data transfer. On the GPIB-
COM this register is implemented as a read-only register. Writing to the line status register will
not change its contents. The function of each bit in this register is explained below.
Bit Mnemonic Description
7r 0 Reserved Bit
This bit always reads as 0.
6r TEMT Transmitter Shift Register Empty Bit
This bit is cleared when a character is transferred from the
Transmitter Holding Register to the Transmitter Shift Register
and set when the character has been shifted out of the Shift
Register onto the serial output line.
On the GPIB-COM, there is no shift register so this bit behaves
exactly the same as the THRE bit.
5r THRE Transmitter Holding Register Empty Bit
This bit is cleared when the processor writes a character into the
Transmitter Holding Register and set when the character has
been transmitted and the INS8250 is ready to send another
character.
This bit functions identically on the GPIB-COM and the
INS8250.
4r BI Break Interrupt Bit
This bit is set to logical 1 when the serial data input remains in
the logical 0 state for longer than one full word transmission
time.
On the GPIB-COM, this bit is always clear.