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Section Five Programming the GPIB-COM
© National Instruments Corporation 5-15 GPIB-COM User Manual
Bit Mnemonic Description
2r TERI Trailing Edge Ring Indicator Bit
This bit is set when the serial port RI input signal changes from
a logical 1 to a logical 0 and cleared when the processor reads
the Modem Status Register.
On the GPIB-COM, this bit is always clear.
1r DDSR Delta Set Ready Bit
This bit is set when the serial port DSR input signal changes
state and cleared when the processor reads the Modem Status
Register.
On the GPIB-COM, this bit is always clear.
0r DCTS Delta Clear to Send Bit
This bit is set when the CTS input changes state and cleared
when the processor reads the Modem Status Register.
On the GPIB-COM, this bit is the logical AND of the DTR and
RTS bits of the Modem Control Register.