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AMD Confidential
User Manual September 12
h
, 2008
186 Appendix A
A.4 CPUID
This section is an overview of the CPUID feature implementation in the AweSim CPU
processor model.
A.4.1 CPUID Standard Feature Support (Standard
Function 0x01)
Table 15-6 shows the standard feature bits returned by the AweSim CPU processor
model and which features are fully ( ) or only partially ( ) implemented and
supported. A indicates that the returned feature bit is zero and this feature is not
implemented and not supported.
Feature
7
th
Generation
8
th
Generation
(Base)
8
th
Generation
Pre.-Rev. F
8
th
Generation
Rev. F
Floating-Point Unit
Virtual Mode Extensions
Debugging Extensions
1
Page-Size Extension
Time Stamp Counter
AMD Model-Specific Registers
Physical-Address Extensions
Machine Check Exception
CMPXCHG8B Instruction
APIC
SYSENTER and SYSEXIT
Memory Type Range Registers
Page Global Extension
Machine Check Architecture
Conditional Move Instruction
Page Attribute Table
Page Size Extensions (PSE-36)
CFLUSH Instruction
MMX™ Instructions
FXSAVE/FXRSTOR
SSE
SSE2
Hyper Threading
SSE3/PNI
Monitor/MWAIT
1
Only read and write to debug registers is supported, side affects are not implemented.