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Reference Design Example
4-2 Copyright © 2001-2003. All rights reserved. ARM DUI 0163B
4.1 About the design example
This chapter describes the reference design example supplied with the interface module.
The interface module is not fitted with any programmable devices because it is intended
to provide interfaces for peripherals instantiated into a logic module FPGA.
The interface module design example for the logic module is supplied in VHDL.
Although the PrimeCell peripherals can be seen instantiated in the top level VHDL file
IMAD1fpga.vhd
, the HDL source code for the PrimeCell peripherals themselves are not
supplied. All other non-PrimeCell HDL source code is provided on the CD.
The design example supports AHB-based designs for Integrator/LM-XCV600E+ and
LM-EP20K600E+ logic modules.
4.1.1 About PrimeCells
The ARM PrimeCell peripherals are a range of synthesizable peripherals that are ideally
suited for use in ARM-based designs. The interface module is supplied with PrimeCell
peripherals for some of the interfaces on the board and the accompanying CD contains
documentation for them.
4.1.2 Example architecture
The architecture of the example is shown in Figure 4-1 on page 4-3. The design
example contains the following peripherals:
• PrimeCell:
—UART
— Synchronous Serial Port (SSP)
— DC-DC converter
— Vectored Interrupt Controller (VIC).
• Non-PrimeCell:
— APB control registers
—GPIO
— Stepper motor interface
— CAN controller interface
— ADC and DAC interface
— Peripheral Information Block (PIB).