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Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition –- March 2000
viii
LIST OF FIGURES
F
IGURE
2–1. C
OMPAQ I
PAQ I
NTERNET
D
EVICE WITH
M
ONITOR
............................................................. 2-1
F
IGURE
2–2. C
OMPAQ I
PAQ I
NTERNET
D
EVICE
, F
RONT
V
IEW
................................................................ 2-4
F
IGURE
2–3. C
OMPAQ I
PAQ I
NTERNET
D
EVICE
, R
EAR
V
IEWS
................................................................ 2-5
F
IGURE
2–4. C
OMPAQ I
PAQ I
NTERNET
D
EVICE
C
HASSIS
L
AYOUT
, R
IDE
S
IDE
V
IEW
................................ 2-6
F
IGURE
2–5. C
OMPAQ I
PAQ S
YSTEM
B
OARD
L
AYOUTS
......................................................................... 2-7
F
IGURE
2–6. C
OMPAQ I
PAQ A
RCHITECTURE
, B
LOCK DIAGRAM
.............................................................. 2-9
F
IGURE
2–7. P
ROCESSOR
A
SSEMBLY AND
M
OUNTING
.......................................................................... 2-11
F
IGURE
3–1. P
ROCESSOR
/M
EMORY
S
UBSYSTEM
A
RCHITECTURE
............................................................ 3-1
F
IGURE
3–2. C
ELERON
P
ROCESSOR
I
NTERNAL
A
RCHITECTURE
............................................................... 3-2
F
IGURE
3–3. P
ENTIUM
III P
ROCESSOR
I
NTERNAL
A
RCHITECTURE
........................................................... 3-3
F
IGURE
3–4. S
YSTEM
M
EMORY
M
AP
..................................................................................................... 3-7
F
IGURE
4-1. PCI B
US
D
EVICES AND
F
UNCTIONS
..................................................................................... 4-2
F
IGURE
4-2. T
YPE
0 C
ONFIGURATION
C
YCLE
......................................................................................... 4-4
F
IGURE
4-3. PCI C
ONFIGURATION
S
PACE
M
AP
...................................................................................... 4-5
F
IGURE
4-4. AGP 1X D
ATA
T
RANSFER
(P
EAK
T
RANSFER
R
ATE
: 266 MB/
S
)........................................... 4-9
F
IGURE
4-5. AGP 2X D
ATA
T
RANSFER
(P
EAK
T
RANSFER
R
ATE
: 532 MB/
S
)......................................... 4-10
F
IGURE
4-6. M
ASKABLE
I
NTERRUPT
P
ROCESSING
, B
LOCK
D
IAGRAM
..................................................... 4-12
F
IGURE
4-7. C
ONFIGURATION
M
EMORY
M
AP
....................................................................................... 4-17
F
IGURE
5-1.
40-P
IN
P
RIMARY
IDE C
ONNECTOR
(
ON SYSTEM BOARD
)...................................................... 5-3
F
IGURE
5-2.
50-P
IN
S
ECONDARY
IDE C
ONNECTOR
(
ON SYSTEM AND DAUGHTER BOARDS
)....................... 5-4
F
IGURE
5-3.
S
ERIAL
I
NTERFACE
C
ONNECTOR
(M
ALE
DB-9
AS VIEWED FROM REAR OF CHASSIS
) ............... 5-5
F
IGURE
5-4.
S
ERIAL
I
NTERFACE
H
EADER
(
ON LEGACY
-
FREE SYSTEM BOARD
)........................................... 5-6
F
IGURE
5-5.
P
ARALLEL
I
NTERFACE
C
ONNECTOR
(F
EMALE
DB-25
AS VIEWED FROM REAR OF CHASSIS
).... 5-14
F
IGURE
5-6.
8042-T
O
-K
EYBOARD
T
RANSMISSION OF
C
ODE
ED
H
, T
IMING
D
IAGRAM
............................. 5-15
F
IGURE
5-7.
K
EYBOARD OR
P
OINTING
D
EVICE
I
NTERFACE
C
ONNECTOR
................................................ 5-21
F
IGURE
5-8.
USB I/F, B
LOCK
D
IAGRAM
............................................................................................... 5-22
F
IGURE
5-9.
USB P
ACKET
F
ORMATS
.................................................................................................... 5-23
F
IGURE
5-10.
U
NIVERSAL
S
ERIAL
B
US
C
ONNECTOR
.............................................................................. 5-25
F
IGURE
5-11.
A
UDIO
S
UBSYSTEM
F
UNCTIONAL
B
LOCK
D
IAGRAM
......................................................... 5-27
F
IGURE
5-12.
AC’97 L
INK
B
US
P
ROTOCOL
.......................................................................................... 5-28
F
IGURE
5-13.
AD1881 A
UDIO
C
ODEC
F
UNCTIONAL
B
LOCK
D
IAGRAM
................................................... 5-29
F
IGURE
5-14.
10/100 TX N
ETWORK
I
NTERFACE
C
ONTROLLER
B
LOCK
D
IAGRAM
................................... 5-32
F
IGURE
5-15.
E
THERNET
TPE C
ONNECTOR
(RJ-45,
VIEWED FROM CARD EDGE
)..................................... 5-36
F
IGURE
6-1. G
RAPHICS
S
UBSYSTEM
B
LOCK DIAGRAM
............................................................................ 6-2
F
IGURE
6-2. 82810
E
/DC-100 I
NTEGRATED
G
RAPHICS
C
ONTROLLER
....................................................... 6-3
F
IGURE
7–1.
P
OWER
D
ISTRIBUTION AND
C
ONTROL
, B
LOCK
D
IAGRAM
..................................................... 7-1
F
IGURE
7–2. P
OWER
C
ABLE
D
IAGRAM
.................................................................................................. 7-4
F
IGURE
7–3. S
IGNAL
D
ISTRIBUTION
D
IAGRAM
....................................................................................... 7-5
F
IGURE
7–4. H
EADER
P
INOUTS
............................................................................................................. 7-6
F
IGURE
B–1. ASCII C
HARACTER
S
ET
...................................................................................................B-1