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Chapter 3 Processor/Memory Subsystem
Compaq iPAQ Family of Internet Devices
First Edition - March 2000
3-8
3.4 SUBSYSTEM CONFIGURATION
The 82810e-DC100 GMCH component provides the configuration function for the
processor/memory subsystem. Table 3-4 lists the configuration registers used for setting and
checking such parameters as memory control and PCI bus operation. These registers reside in the
PCI Configuration Space and accessed using the methods described in Chapter 4, section 4.2.
Table 3–4.
Host/PCI Bridge Configuration Registers (GMCH, Function 0)
Table 3-4.
Host/PCI Bridge Configuration Registers (GMCH, Function 0)
PCI Config.
Addr. Register
Reset
Value
PCI Config.
Addr. Register
Reset
Value
00, 01h Vender ID 8086h 6A, 6Bh DRAM Control Reg. 00h
02, 03h Device ID 7190h 6C..6Fh Memory Buffer Strength 55h
04, 05h Command 0006h 70h Multi-Transaction Timer 00h
06, 07h Status 0210h 71h CPU Latency Timer 10h
08h Revision ID -- 72h SMRAM Control 02h
09..0Bh Class Code -- 90h Error Command 00h
0Dh Latency Timer 00h 91h Error Status Register 0 00h
0Eh Header Type 00h 92h Error Status Register 1 00h
10..13h Aperture Base Config. 8 93h Reset Control 00h
50, 51h PAC Config. Reg. 00h A0..A3h AGP Capability Identifier N/A
53h Data Buffer Control 83h A4..A7h AGP Status N/A
55..56h DRAM Row Type 00h A8..ABh AGP Command 00h
57h DRAM Control 01h B0..B3h AGP Control 00h
58h DRAM Timing 00h B4h Aperture Size 0000h
59..5Fh PAM 0..6 Registers 00h B8..BBh Aperture Translation Table 0000h
60..67h DRAM Row Boundary 01h BCh Aperture I/F Timer 00h
68h Fixed DRAM Hole 00h BDh Low Priority Timer 00h
NOTES:
Refer to Intel Inc. documentation for detailed description of registers.
Assume unmarked locations/gaps as reserved.