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Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition –- March 2000
x
LIST OF TABLES
T
ABLE
1–1. A
CRONYMS AND
A
BBREVIATIONS
....................................................................................... 1-3
T
ABLE
2-1. F
EATURE
D
IFFERENCE
M
ATRIX
........................................................................................... 2-2
T
ABLE
2-2. A
RCHITECTURAL
C
OMPARISON
............................................................................................. 2-8
T
ABLE
2-3. I
NTEL
810
E
C
HIPSET
C
OMPARISON
.................................................................................... 2-12
T
ABLE
2-4. S
UPPORT
C
OMPONENT
F
UNCTIONS
.................................................................................... 2-13
T
ABLE
2-5. E
NVIRONMENTAL
S
PECIFICATIONS
.................................................................................... 2-15
T
ABLE
2-6. E
LECTRICAL
S
PECIFICATIONS
............................................................................................ 2-15
T
ABLE
2-7. P
HYSICAL
S
PECIFICATIONS
................................................................................................ 2-16
T
ABLE
2-8. M
ULTI
B
AY
24
X
CD-ROM D
RIVE
S
PECIFICATIONS
............................................................. 2-16
T
ABLE
2-9. M
ULTI
B
AY
24
X
CD-ROM D
RIVE
S
PECIFICATIONS
............................................................. 2-17
T
ABLE
2-10. H
ARD
D
RIVE
S
PECIFICATIONS
......................................................................................... 2-17
T
ABLE
3–1. C
ELERON
P
ROCESSOR
S
TATISTICAL
C
OMPARISON
............................................................... 3-2
T
ABLE
3–2. P
ENTIUM
III P
ROCESSOR
S
TATISTICAL
C
OMPARISON
........................................................... 3-3
T
ABLE
3–3. SPD A
DDRESS
M
AP
(SDRAM DIMM)................................................................................. 3-6
T
ABLE
3–4. H
OST
/PCI B
RIDGE
C
ONFIGURATION
R
EGISTERS
(GMCH, F
UNCTION
0)................................ 3-8
T
ABLE
4-1. PCI D
EVICE
C
ONFIGURATION
A
CCESS
................................................................................. 4-4
T
ABLE
4-2. S
YSTEM
B
OARD
PCI D
EVICE
I
DENTIFICATION
..................................................................... 4-5
T
ABLE
4-3. LPC B
RIDGE
C
ONFIGURATION
R
EGISTERS
(ICH, F
UNCTION
0).............................................. 4-7
T
ABLE
4-4. PCI/AGP B
RIDGE
C
ONFIGURATION
R
EGISTERS
(MCH, F
UNCTION
1) ..................................4-11
T
ABLE
4-5. M
ASKABLE
I
NTERRUPT
P
RIORITIES AND
A
SSIGNMENTS
...................................................... 4-13
T
ABLE
4-6. M
ASKABLE
I
NTERRUPT
C
ONTROL
R
EGISTERS
.................................................................... 4-13
T
ABLE
4-7. I
NTERVAL
T
IMER
F
UNCTIONS
............................................................................................ 4-16
T
ABLE
4-8. I
NTERVAL
T
IMER
C
ONTROL
R
EGISTERS
............................................................................. 4-16
T
ABLE
4-9. C
LOCK
G
ENERATION AND
D
ISTRIBUTION
........................................................................... 4-16
T
ABLE
4-10. C
ONFIGURATION
M
EMORY
(CMOS) M
AP
....................................................................... 4-18
T
ABLE
4-11. S
YSTEM
I/O M
AP
........................................................................................................... 4-29
T
ABLE
5–1. IDE PCI C
ONFIGURATION
R
EGISTERS
................................................................................ 5-2
T
ABLE
5–2.
IDE B
US
M
ASTER
C
ONTROL
R
EGISTERS
.............................................................................. 5-2
T
ABLE
5–3. 40-P
IN
P
RIMARY
IDE C
ONNECTOR
P
INOUT
......................................................................... 5-3
T
ABLE
5–4. 50-P
IN
S
ECONDARY
IDE C
ONNECTOR
P
INOUT
.................................................................... 5-4
T
ABLE
5–5.
DB-9 S
ERIAL
C
ONNECTOR
P
INOUT
...................................................................................... 5-5
T
ABLE
5–6. S
ERIAL
I
NTERFACE
C
ONFIGURATION
R
EGISTERS
.................................................................. 5-6
T
ABLE
5–7. S
ERIAL
I
NTERFACE
C
ONTROL
R
EGISTERS
............................................................................ 5-7
T
ABLE
5–8. P
ARALLEL
I
NTERFACE
C
ONFIGURATION
R
EGISTERS
........................................................... 5-10
T
ABLE
5–9.
P
ARALLEL
I
NTERFACE
C
ONTROL
R
EGISTERS
...................................................................... 5-11
T
ABLE
5–10. DB-25 P
ARALLEL
C
ONNECTOR
P
INOUT
.......................................................................... 5-14
T
ABLE
5–11. 8042-T
O
-K
EYBOARD
C
OMMANDS
.................................................................................. 5-16
T
ABLE
5–12. K
EYBOARD
I
NTERFACE
C
ONFIGURATION
R
EGISTERS
....................................................... 5-17
T
ABLE
5–13. CPU C
OMMANDS
T
O
T
HE
8042...................................................................................... 5-19
T
ABLE
5–14. K
EYBOARD
/P
OINTING
D
EVICE
C
ONNECTOR
P
INOUT
........................................................ 5-21
T
ABLE
5–15. USB I
NTERFACE
C
ONFIGURATION
R
EGISTERS
................................................................. 5-24
T
ABLE
5–16. USB C
ONTROL
R
EGISTERS
............................................................................................. 5-24
T
ABLE
5–17. USB C
ONNECTOR
P
INOUT
.............................................................................................. 5-25
T
ABLE
5–18. USB C
ABLE
L
ENGTH
D
ATA
............................................................................................ 5-25