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Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition - March 2000
3-1
Chapter 3
PROCESSOR/
MEMORY SUBSYSTEM
3.
Chapter 3 PROCESSOR/MEMORY SUBSYSTEM
3.1 INTRODUCTION
This chapter describes the processor/cache memory subsystem of the Compaq iPAQ Internet
Device featuring a Celeron or Pentium III processor and the 810e chipset (Figure 3-1). The 810e
chipset supports up to two SDRAM DIMMs and integrates an i740 3D graphics controller
(covered in Chapter 6).
Figure 3–1.
Processor/Memory Subsystem Architecture
This chapter includes the following topics:
♦
Processor [3.2] page 3-2
♦
Memory subsystem [3.3] page 3-5
♦
Subsystem configuration {3.4] page 3-8
Processor
64-Bit FSB
Cntl
100-MHz
Memory Bus
32-MB
DIMM
In
Socket
J1
J2
System Memory
Socket
82810e-DC100
GMCH
FSB I/F
i740
Graphics
Cntlr.
SDRAM
Cntlr.
Hub I/F
May be populated with optional DIMM
Covered in Chapter 6
Covered in Chapter 4