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Chapter 4 System Support
Compaq iPAQ Family of Internet Devices
First Edition - March 2000
4-2
4.2 PCI BUS OVERVIEW
NOTE:
This section describes the PCI bus in general and highlights bus
implementation in this particular system. For detailed information regarding PCI bus
operation, refer to the PCI Local Bus Specification Revision 2.2.
This system implements a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2)
operating at 33 MHz. The PCI bus handles address/data transfers through the identification of
devices and functions on the bus. A device is typically defined as a component that resides on the
PCI bus (although some components such as the GMCH and ICH are organized as multiple
devices). A function is defined as the end source or target of the bus transaction. A device may
contain one or more functions.
This system use two PCI buses. The PCI bus #0 is internal to the 810e chipset and divided by the
hub link bus. The PCI bus #1 is used by the NIC function (Figure 4-1). As this system is designed
for simplicity of system management,
the PCI buses are not available for expansion purposes.
Figure 4-1.
PCI Bus Devices and Functions
Hub Link Bus
PCI Bus #1
82810e GMCH
Component
AGP
Bridge
Function
Memory
Controller
Function
PCI Bus #0
82801 ICH Component
EIDE
Controller
Function
Hub Link/PCI
Bridge
Function
USB
I/F
Function
SMBus
Controller
Function
LPC
Bridge
Function
AC97
Audio
Function
PCI Bus #0
82559
NIC
I/F
Function