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Technical Reference Guide
Compaq iPAQ Family of Internet Devices
First Edition –- March 2000
iv
CHAPTER 4 SYSTEM SUPPORT.........................................................................................................
4.1 INTRODUCTION.................................................................................................................. 4-1
4.2 PCI BUS OVERVIEW........................................................................................................... 4-2
4.2.1 PCI BUS TRANSACTIONS........................................................................................... 4-3
4.2.2 PCI INTERRUPT MAPPING......................................................................................... 4-6
4.2.3 PCI POWER MANAGEMENT SUPPORT..................................................................... 4-6
4.2.4 PCI SUB-BUSSES.......................................................................................................... 4-6
4.2.5 PCI CONFIGURATION................................................................................................. 4-7
4.3 AGP BUS OVERVIEW ......................................................................................................... 4-8
4.3.1 BUS TRANSACTIONS.................................................................................................. 4-8
4.3.2 AGP CONFIGURATION ............................................................................................. 4-11
4.4 INTERRUPTS ..................................................................................................................... 4-12
4.4.1 MASKABLE INTERRUPTS........................................................................................ 4-12
4.4.2 NON-MASKABLE INTERRUPTS............................................................................... 4-14
4.5 INTERVAL TIMER............................................................................................................. 4-16
4.6 SYSTEM CLOCK DISTRIBUTION.................................................................................... 4-16
4.7 REAL-TIME CLOCK AND CONFIGURATION MEMORY............................................... 4-17
4.7.1 CMOS ARCHIVE ........................................................................................................ 4-18
4.7.2 STANDARD CMOS LOCATIONS.............................................................................. 4-18
4.7.3 CMOS FEATURE BITS............................................................................................... 4-26
4.8 SYSTEM MANAGEMENT................................................................................................. 4-27
4.8.1 SECURITY FUNCTIONS............................................................................................ 4-27
4.8.2 POWER MANAGEMENT ........................................................................................... 4-28
4.8.3 THERMAL SENSING AND COOLING ...................................................................... 4-28
4.9 SYSTEM I/O MAP.............................................................................................................. 4-29
CHAPTER 5 INPUT/OUTPUT INTERFACES.....................................................................................
5.1 INTRODUCTION.................................................................................................................. 5-1
5.2 ENHANCED IDE INTERFACE............................................................................................ 5-1
5.2.1 IDE PROGRAMMING................................................................................................... 5-1
5.2.2 IDE CONNECTOR ........................................................................................................ 5-3
5.3 DISKETTE DRIVE INTERFACE.......................................................................................... 5-4
5.4 SERIAL INTERFACE ...........................................................................................................5-5
5.4.1 RS-232 INTERFACE ..................................................................................................... 5-5
5.4.2 SERIAL TEST INTERFACE ........................................................................................ 5-6
5.4.3 SERIAL INTERFACE PROGRAMMING...................................................................... 5-6
5.5 PARALLEL INTERFACE .....................................................................................................5-8
5.5.1 STANDARD PARALLEL PORT MODE ....................................................................... 5-8
5.5.2 ENHANCED PARALLEL PORT MODE.......................................................................5-9
5.5.3 EXTENDED CAPABILITIES PORT MODE................................................................. 5-9
5.5.4 PARALLEL INTERFACE PROGRAMMING.............................................................. 5-10
5.5.5 PARALLEL INTERFACE CONNECTOR ................................................................... 5-14
5.6 KEYBOARD/POINTING DEVICE INTERFACE ............................................................... 5-15
5.6.1 KEYBOARD INTERFACE OPERATION ................................................................... 5-15
5.6.2 POINTING DEVICE INTERFACE OPERATION ....................................................... 5-17
5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING ......................... 5-17
5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR................................ 5-21