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NTBK50 2.0 Mb PRI card Page 497 of 544
Option 11C and 11C Mini Technical Reference Guide
• clock controller interface
• Card-LAN / echo / test port interface
• 80C51FA Microcontroller
A description of each block follows.
DS-30X interface
NTBK50 interfaces to one DS-30X bus which contains 32 byte-interleaved
timeslots operating at 2.56 Mb. Each timeslot contains 10 bits in A10
message format; 8 are assigned to voice/data (64 Kbps), one to signaling
(8 Kbps), and one is a data valid bit (8 Kbps).
The incoming serial bit stream is converted to 8-bit parallel bytes to be
directed to padding control. The signaling bits are extracted and inserted by
the A07 signaling interface circuitry. Timeslots 0 and 16 are currently unused
for PCM.
Digital PAD
Software selects A-law or Mu-Law and one of 32 possible PAD values for
each channel. These values are provided in a PROM through which the data
is routed. The idle code for A-law is 54H and for Mu-law is 7FH. The
unequipped code is FFH for both A-law and Mu-law.
As the idle code and unequipped code may be country dependent, the
software instructs the NTBK50 to use different codes for each direction. The
32 digital pads available are illustrated in Table 154 on page 498. The values
shown are attenuation levels (1.0dB is 1dB of loss and -1.0dB is 1db of gain).