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Si53xx-RM
Rev. 0.5 19
3.3. Si5322
The Si5322 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter
attenuation. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two frequency-
multiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency and clock multiplication ratio
are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video (HD SDI, 3G SDI)
rates. The DSPLL loop bandwidth is digitally selectable from 150 kHz to 1.3 MHz. Operating from a single 1.8, 2.5,
or 3.3 V supply, the Si5322 is ideal for providing low jitter clock multiplication in high performance timing
applications. See "6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)" on page 50 for a complete
description.
Figure 3. Si5322 Low Jitter Clock Multiplier Block Diagram
DSPLL
®
C1B
CS_CA
BWSEL[1:0]
DBL2_BY
SFOUT[1:0]
CKOUT_2+
CKOUT_2–
CKIN_1+
CKIN_1–
CKOUT_1+
CKOUT_2–
CKIN_2+
CKIN_2–
Control
AUTOSEL
FRQTBL
Signal
Detect
VDD
GND
Frequency
Control
Bandwidth
Control
C2B
2
2
FRQSEL[3:0]
RST
0
1
f
OSC
2
2
0
1
0
1
f
3