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Si53xx-RM
Rev. 0.5 79
The output divider, NC1, is the product of a high-speed divider (N1_HS) and a low-speed divider (N1_LS).
Similarly, the feedback divider N2 is the product of a high-speed divider N2_HS and a low-speed divider N2_LS.
When multiple combinations of high-speed and low-speed divider values are available to produce the desired
overall result, selecting the largest possible high-speed divider value will produce lower power consumption. With
the f
OSC
and N1 ranges given above, any output frequency can be achieved from 2 kHz to 945 MHz where NC1
ranges from (4 x 220) to 6. For NC1 = 5, the output frequency range 970 MHz to 1.134 GHz can be obtained. For
NC1 = 4, the output frequency range from 1.2125 to 1.4175 GHz is available.
Because there is only one DCO and all of the outputs must be frequencies that are integer divisions of the DCO
frequency, there are restrictions on the ratio of one output frequency to another output frequency. That is, there is
considerable freedom in the ratio between the input frequency and the first output frequency; but once the first
output frequency is chosen, there are restrictions on subsequent output frequencies. These restrictions are caused
by the fact that the N1_HS divider is shared among all of the outputs. DSPLLsim should be used to determine if two
different simultaneous outputs are compatible with one another.
The same issue exists for inputs of different frequency: both inputs, after having been divided by their respective
N3 dividers, must result in the same f3 frequency because the phase/frequency detector can operate at only one
frequency at one time.
7.1.4. Loop Bandwidth (Si5319, Si5326, Si5368, Si5375)
The device functions as a jitter attenuator with digitally programmable loop bandwidth (BW). The loop bandwidth
settings range from 60 Hz to 8.4 kHz and are set using the BWSEL_REG[3:0] register bits. The device operating
frequency should be determined prior to loop bandwidth configuration because the loop bandwidth is a function of
the phase detector input frequency and the PLL feedback divider. See DSPLLsim for a table of BWSEL_REG and
associated loop bandwidth settings. For more information the loop BW and its effect on jitter attenuation, see
"Appendix H—Jitter Attenuation and Loop BW" on page 164.
7.1.4.1. Low Loop Bandwidth (Si5324, Si5327, Si5369, Si5374)
The loop BW of the Si5324, Si5327, Si5369, and Si5374 is significantly lower than the BW of the Si5326. The
available Si5324/27/69/74 loop bandwidth settings and their register control values for a given frequency plan are
listed by DSPLLsim (Revision 4.0.1 or higher) or in Si537xDSPLLsim. Compared to the Si5326, the BW Si5324/27/
69/74 settings are approximately 16 times lower, which means that the Si5324/27/69/74 loop bandwidth ranges
from about 4 to 525 Hz.
7.1.5. Lock Detect (Si5319, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
The device has a PLL lock detection algorithm that indicates the lock status on the LOL output pin and the
LOL_INT read-only register bit. See Section “7.11.8. LOL (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369,
Si5374, Si5375)” for a detailed description of the LOL algorithm.
7.2. PLL Self-Calibration
The device performs an internal self-calibration before operation to optimize loop parameters and jitter
performance. While the self-calibration is being performed, the DCO is being internally controlled by the self-
calibration state machine, and the LOL alarm will be active. The output clocks can either be active or disabled
depending on the SQ_ICAL bit setting. The self-calibration time t
LOCKMP
is given in Table 8, “AC Characteristics—
All Devices”. The procedure for initiating the internal self-calibration is described below.
7.2.1. Initiating Internal Self-Calibration
Any of the following events will trigger an automatic self-calibration:
Internal DCO registers out-of-range, indicating the need to relock the DCO
Setting the ICAL register bit to 1
In any of the above cases, an internal self-calibration will be initiated if a valid input clock exists (no input alarm)
and is selected as the active clock at that time. The external crystal or reference clock must also be present for the
self-calibration to begin (LOSX_INT = 0 [narrowband only]).
When self-calibration is initiated the device generates an output clock if the SQ_ICAL bit is set to 0. The output
clock will appear when the device begins self-calibration. The frequency of the output clocks may be as high as 5%
above or as low as 20% below the final locked value. If SQ_ICAL = 1, the output clocks are disabled during self-