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Si53xx-RM
94 Rev. 0.5
For cases where phase skew is required, see Section “7.7. Output Phase Adjust (Si5326, Si5368)” for more details
on controlling the sync input to sync output phase skew via the FSYNC_SKEW[16:0] bits. See Section “8.2. Output
Clock Drivers” for information on the FS_OUT signal format, pulse width, and active logic level control.
7.8.2. FSYNC Skew Control (Si5368)
When CKIN3 and CKIN4 are configured as frame sync inputs (CK_CONFIG_REG = 1), phase skew of the sync
input active edge to FS_OUT active edge is controllable via the FSYNC_SKEW[16:0] register bits. Skew control
has a resolution of 1/f
CKOUT2
and a range of 131,071/f
CKOUT2
. The entered skew value must be less than the
period of CKIN3, CKIN4, and FS_OUT.
The skew should not be changed more than once per FS_OUT period. If a FSYNC realignment is being made, the
skew should not be changed until the realignment is complete. The skew value and the FS_OUT pulse width
should not be changed within the same FS_OUT period.
Before writing the three bytes needed to specify a new FSYNC_SKEW[16:0] value, the user should set the register
bit FSKEW_VALID = 0. This causes the alignment state machine to keep using the previous FSYNC_SKEW[16:0]
value, ignoring the new register values as they are being written. Once the new FSYNC_SKEW[16:0] value has
been completely written, the user should set FSKEW_VALID = 1 at which time the alignment state machine will
read the new skew alignment value. Note that when the new FSYNC_SKEW[16:0] value is used, a phase step will
occur in FS_OUT.
7.8.3. Including FSYNC Inputs in Clock Selection (Si5368)
The frame sync inputs, CKIN3 and CKIN4, are both monitored for loss-of-signal (LOS3_INT and LOS4_INT)
conditions. To include these LOS alarms in the input clock selection algorithm, set FSYNC_SWTCH_REG =1. The
LOS3_INT is logically ORed with LOS1_INT and LOS4_INT is ORed with LOS2_INT as inputs to the clock
selection state machine. If it is desired not to include these alarms in the clock selection algorithm, set
FSYNC_SWTCH_REG = 0. The frequency offset (FOS) alarms for CKIN1 and CKIN2 can also be included in the
state machine decision making as described in Section “7.11. Alarms (Si5319, Si5324, Si5325, Si5326, Si5327,
Si5367, Si5368, Si5369, Si5374, Si5375)”; however, in frame sync mode (CK_CONFIG_REG = 1), the FOS alarms
for CKIN3 and CKIN4 are ignored.
7.8.4. FS_OUT Polarity and Pulse Width Control (Si5368)
Additional output controls are available for FS_OUT. The active polarity of FS_OUT is set via the FS_OUT_POL
register bit and the active duty cycle is set via the FSYNC_PW[9:0] register. Pulse width settings have a resolution
of 1/f
CKOUT2
, and a 50% duty cycle setting is provided. Pulse width settings can range from 1 to (NC5-1) CKOUT2
periods, providing the full range of pulse width possibilities for a given NC5 divider setting.
The FS_OUT pulse should not be changed more than once per FS_OUT period. If a FSYNC realignment is being
made, the pulse width should not be changed until the realignment is complete. The FS_OUT pulse width and the
skew value should not be changed within the same FS_OUT period.
Before writing a new value into FSYNC_PW[9:0], the user should set the register bit FPW_VALID = 0. This causes
the FS_OUT pulse width state machine to keep using the previous FSYNC_PW[9:0] value, ignoring the new
register values as they are being written. Once the new FSYNC_PW[9:0] value has been completely written, the
user should set FPW_VALID = 1, at which time the FS_OUT pulse width state machine will read the new pulse
width value.
Writes to NC5_LS should be treated the same as writes to FSYNC_PW. Thus, all writes to NC5_LS should occur
only when FPW_VALID = 0. Any such writes will not take effect until FPW_VALID = 1.
Note that f
CKOUT2
must be less than or equal to 710 MHz when CK_CONFIG_REG = 1; otherwise, the FS_OUT
buffer and NC5 divider must be disabled.
7.8.5. Using FS_OUT as a Fifth Output Clock (Si5368)
In applications where the frame synchronization functionality is not needed (CK_CONFIG_REG = 0), FS_OUT can
be used as a fifth clock output. In this case, no realignment requests should be made to the NC5 divider (hold
FS_ALIGN = 0 and FSYNC_ALIGN_REG = 0). Output pulse width and polarity controls for FS_OUT are still
available as described above. The 50% duty cycle setting would be used to generate a typical balanced output
clock.