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Si53xx-RM
Rev. 0.5 97
7.11.1.2. Standard LOS (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
To facilitate automatic hitless switching, the LOS trigger time can be significantly reduced by using the default LOS
option (LOSn_EN = 11). The LOS circuitry divides down each input clock to produce a 2 kHz to 2 MHz signal. The
LOS circuitry over samples this divided down input clock using a 40 MHz clock to search for extended periods of
time without input clock transitions. If the LOS monitor detects twice the normal number of samples without a clock
edge, an LOS alarm is declared. The LOSn trigger window is based on the value of the input divider N3. The value
of N3 is reported by DSPLLsim.
The range over which LOS is guaranteed to not produce false positive assertions is 100 ppm. For example, if a
device is locked to an input clock on CKIN1, the frequency of CKIN2 should differ by no more than 100 ppm to
avoid false LOS2 assertions.
The frequency range over which FOS monitoring may occur is from 10 to 710 MHz.
7.11.1.3. LOSA (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
A slower response version of LOS called LOSA is available and should be used under certain conditions. Because
LOSA is slower and less sensitive than LOS, its use should be considered for applications with quasi-periodic
clocks (e.g., gapped clocks with one or more consecutive clock edges removed), when switching between input
clocks with a large difference in frequency and any other application where false positive assertions of LOS may
incorrectly cause the Any-Frequency device to be forced into Digital Hold.
For example, it is recommended that while in Free Run Mode LOSA be used instead of LOS because the two clock
inputs will not be the same exact frequency. This will avoid false LOS assertions when the XA/XB frequency differs
from the other clock inputs by more than 100 ppm. See Section 7.11.1.3 for more information on LOSA.
7.11.1.4. LOS disabled (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
For situations where no form of LOS is desired, LOS can be disabled by writing 00 to LOSn_EN. This mode is
provided to support applications which implement custom LOS algorithms off-chip. If this approach is taken, the
only remaining methods of entering Digital Hold will be FOS or by setting DHOLD (register 3, bit 5).
7.11.1.5. Wideband LOS Algorithm (Si5322, Si5365)
Each input clock is divided down to produce a 78 kHz to 1.2 MHz signal before entering the LOS monitoring
circuitry. The same LOS algorithm as described in the above section is then used. FOS is not available in wideband
devices.
7.11.1.6. LOS Alarm Outputs (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5369, Si5374, Si5375)
When LOS is enabled, an LOS condition on CKIN1 causes LOS1_INT to become active. Similarly, when LOS is
enabled, an LOS condition on CKIN2 causes LOS2_INT to become active. Once a LOSn_INT alarm is asserted on
one of the input clocks, it remains asserted until the input clock is validated over a designated time period. If
another error condition on the same input clock is detected during the validation time then the alarm remains
asserted and the validation time starts over.
7.11.2. FOS Algorithm (Si5324, Si5325, Si5326, Si5368, Si5369, Si5374)
The frequency offset (FOS) alarms indicate if the input clocks are within a specified frequency range relative to the
frequency of a reference clock. The reference clock can be provided by any of the four input clocks (two for Si5324,
Si5325 or Si5326) or the XA/XB input. The default FOS reference is CKIN2. The frequency monitoring circuitry
compares the frequency of the input clock(s) with the FOS reference clock If the frequency offset of an input clock
exceeds a selected frequency offset threshold, an FOS alarm (FOS_INT register bit) is declared for that clock
input. Be aware that large amounts of wander can cause false FOS alarms.
Note: For the Si5368, If CK_CONFIG_REG = 1, only CKIN1 and CKIN2 are monitored; CKIN3 and CKIN4 are used for
FSYNC and are not monitored.
The frequency offset threshold is selectable using the FOS_THR[1:0] bits. Settings are available for compatibility
with SONET Minimum Clock (SCMD) or Stratum 3/3E requirements. See Table 8 on page 40. The device supports
FOS hystereses per GR-1244-CORE, making the device less susceptible to FOS alarm chattering. A reference
clock with suitable accuracy and drift specifications to support the intended application should be used. The FOS
reference clock is set via the FOSREFSEL[2:0] bits as shown in Table 50. More than one input can be monitored
against the FOS reference, i.e., there can be more than one monitored clock, but only one FOS reference. When
the XA/XB input is used as the FOS reference, there is only one reference frequency band that is allowed: from
37 MHz to 41 MHz.