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Si53xx-RM
90 Rev. 0.5
7.7. Output Phase Adjust (Si5326, Si5368)
The device has a highly accurate, digitally controlled device skew capability. For more information on Output Phase
Adjustments, see both DSPLLsim and the respective data sheets. Both can be downloaded by going to
www.silabs.com/timing and clicking on “Documentation” at the bottom of the page.
7.7.1. Coarse Skew Control (Si5326, Si5368)
With the INCDEC_PIN register bit set to 0 (pin control off), overall device skew is controlled via the CLAT[7:0]
register bits. This skew control has a resolution of 1/f
OSC
, approximately 200 ps, and a range from –25.6 to
25.4 ns. Following a powerup or reset (RST
pin or RST_REG register bit), the skew will revert to the reset value.
Any further changes made in the skew register will be read and compared to the previously held value. The
difference will be calculated and applied to the clock outputs. All skew changes are made in a glitch-free fashion.
When a phase adjustment is in progress, any new CLAT[7:0] values are ignored until the update is complete. The
CLATPROG register bit is set to 1 during a coarse skew adjustment. The time for an adjustment to complete is
dependent on bandwidth and the delta value in CLAT. To verify a written value into CLAT, the CLAT register should
be read after the register is written. The time that it takes for the effects of a CLAT change to complete is
proportional to the size of the change, at 83 msec for every unit change, assuming the lowest available loop
bandwidth was selected. For example, if CLAT is zero and has the value 100 written to it, the changes will
complete in
100 x 83 msec = 8.3 sec.
If it is necessary to set the high-speed output clock divider N1_HS to divide-by-4 in order to achieve the desired
overall multiplication ratio and output frequency, only phase increments are allowed and negative settings in the
CLAT register or attempts to decrement the phase via writes to the CLAT register will be ignored. Because of this
restriction, when there is a choice between using N1_HS = 4 and another N1_HS value that can produce the
desired multiplication ratio, the other N1_HS value should be selected. This restriction also applies when using the
INC pin.
With the INCDEC_PIN register bit set to 1 (pin control on), the INC and DEC pins function the same as they do for
pin controlled parts. See "6.6. Output Phase Adjust (Si5323, Si5366)" on page 71.
7.7.1.1. Unlimited Coarse Skew Adjustment (Si5326, Si5368)
Using the following procedure, the CLAT register can be used to adjust the device clock output phase to an
arbitrarily large value that is not limited by the size of the CLAT register:
1. Write a phase adjustment value to the CLAT register (Register 16). The DSPLLsim configuration software
provides the size of a single step.
2. Wait until CLATPROGRESS = 0 (register 130, bit 7), which indicates that the adjustment is complete (Maximum
time for adjustment: 20 seconds for the Si5326 or Si5368).
3. Set INCDEC_PIN = 1 (Register 21, bit 7).
4. Write 0 to CLAT register (Register 16).
5. Wait until CLATPROGRESS =0.
6. Set INCDEC_PIN =0.
7. Repeat the above process as many times as desired.
Steps 3-6 will clear the CLAT register without changing the output phase. This allows for unlimited output clock
phase adjustment using the CLAT register and repeating steps 1–3 as many times as needed.
Note: The INC and DEC pins must stay low during this process.
7.7.2. Fine Skew Control (Si5326, Si5368)
An additional fine adjustment of the overall device skew can be used in conjunction with the INC and DEC pins or
the CLAT[7:0] register bits to provide finer resolution output phase adjustments. Fine phase adjustment is available
using the FLAT[14:0] bits. The nominal range and resolution of the FLAT[14:0] skew adjustment word are:
Range FLAT = ±110 ps
Resolution FLAT = 9 ps