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Architecture
Table 3. Description of the Asynchronous Configuration Register (ACFGn) (continued)
Parameter Description
ASIZE Asynchronous Device Bus Width.
This field determines the data bus width of the asynchronous interface in the following way:
• ASIZE = 0 selects an 8-bit bus
• ASIZE = 1 selects a 16-bit bus
The configuration of ASIZE determines the function of the EM_A and EM_BA pins as described in
Section 2.5.1. This field also determines the number of external accesses required to fulfill a request
generated by one of the sources mentioned in Section 2.2. For example, a request for a 32-bit word
would require four external access when ASIZE = 0h. Refer to the datasheet of the external
asynchronous device to determine the appropriate setting for this field.
Table 4. Description of the Asynchronous Wait Cycle Configuration Register (AWCCR)
Parameter Description
WPn WAIT Polarity.
• WPn = 0 selects active-low polarity
• WPn = 1 selects active-high polarity
When set to 1, the EMIF will wait if the EM_WAITn pin is high. When cleared to 0, the EMIF will wait if the
EM_WAITn pin is low. The EMIF must have the Extended Wait mode enabled (EW bit in the asynchronous
configuration register (ACFGn) is set to 1) for the EM_WAITn pin to affect the width of the strobe period.
MEWC Maximum Extended Wait Cycles.
This field configures the number of EMIF clock cycles the EMIF will wait for the EM_WAITn pin to be deactivated
during the strobe period of an access cycle. The maximum number of EMIF clock cycles the EMIF will wait is
determined by the following formula:
Maximum Extended Wait Cycles = (MEWC + 1) × 16
If the EM_WAITn pin is not deactivated within the time specified by this field, the EMIF resumes the access cycle,
registering whatever data is on the bus and preceding to the hold period of the access cycle. This situation is
referred to as an asynchronous timeout. An asynchronous timeout generates an interrupt if it has been enabled in
the EMIF interrupt mask set register (EIMSR). Refer to Section 2.5.11 for more information about the EMIF
interrupts.
Table 5. Description of the EMIF Interrupt Mask Set Register (EIMSR)
Parameter Description
WRMSETn Wait Rise Mask Set.
Writing a 1 enables an interrupt to be generated when a rising edge on EM_WAITn occurs.
ATMSET Asynchronous Timeout Mask Set.
Writing a 1 to this bit enables an interrupt to be generated when an asynchronous timeout occurs.
Table 6. Description of the EMIF Interrupt Mast Clear Register (EIMCR)
Parameter Description
WRMCLRn Wait Rise Mask Clear.
Writing a 1 to this bit disables the interrupt, clearing the WRMSETn bit in the EMIF interrupt mask set register
(EIMSR).
ATMCLR Asynchronous Timeout Mask Clear.
Writing a 1 to this bit disables the interrupt, clearing the ATMSET bit in the EMIF interrupt mask set register
(EIMSR).
13
SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF)
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