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Preface ....................................................................................................................................... 6
1 Introduction ........................................................................................................................ 8
1.1 Purpose of the Peripheral .............................................................................................. 8
1.2 Features .................................................................................................................. 8
1.3 Functional Block Diagram .............................................................................................. 9
2 Architecture ........................................................................................................................ 9
2.1 Clock Control ............................................................................................................. 9
2.2 EMIF Requests .......................................................................................................... 9
2.3 Signal Descriptions .................................................................................................... 10
2.4 Pin Multiplexing ........................................................................................................ 10
2.5 Asynchronous Controller and Interface ............................................................................. 10
3 Use Cases ........................................................................................................................ 30
3.1 Interfacing to Asynchronous SRAM (ASRAM) ..................................................................... 30
3.2 Interfacing to NAND Flash ............................................................................................ 39
4 Registers .......................................................................................................................... 48
4.1 Revision Code and Status Register (RCSR) ....................................................................... 49
4.2 Asynchronous Wait Cycle Configuration Register (AWCCR) .................................................... 50
4.3 Asynchronous n Configuration Registers (A1CR-A4CR) ......................................................... 52
4.4 EMIF Interrupt Raw Register (EIRR) ................................................................................ 53
4.5 EMIF Interrupt Mask Register (EIMR) ............................................................................... 54
4.6 EMIF Interrupt Mask Set Register (EIMSR) ........................................................................ 56
4.7 EMIF Interrupt Mask Clear Register (EIMCR) ..................................................................... 58
4.8 NAND Flash Control Register (NANDFCR) ........................................................................ 60
4.9 NAND Flash Status Register (NANDFSR) ......................................................................... 61
4.10 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) ................................................... 61
Appendix A Revision History ...................................................................................................... 63
3
SPRUEQ7C–February 2010 Table of Contents
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