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2.5.11.2 Interrupt Multiplexing
The EMIF interrupt is supported by both the ARM and DSP. The interrupt is not multiplexed with another
interrupt and is therefore always available.
2.5.12 Program Execution
Since the EMIF does not have byte enable or data mask pins, byte accesses to memory are not
supported when the data bus width is equal to 16 bits. When performing data accesses on a 16-bit bus,
this may be worked around by performing a write modify read back operation. When executing code from
the EMIF, the bus width must be configured to be an 8-bit data bus.
2.5.13 Power Management
Power dissipation to the EMIF may be managed by gating the input clock to the EMIF off. The input clock
is turned off outside of the EMIF through the use of the Power and Sleep Controller (PSC). When the PSC
sends a clock stop request to the EMIF, the EMIF will complete pending transfers before issuing a clock
stop acknowledge, allowing the PSC to stop the clock. See the TMS320DM646x DMSoC ARM Subsystem
Reference Guide (SPRUEP9) for more information.
2.5.14 Emulation Considerations
The operation of the EMIF is not affected when a breakpoint is reached or an emulation halt occurs.
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SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF)
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