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Registers
Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions (continued)
Bit Field Value Description
0 ATMSET Asynchronous Timeout Mask Set. This bit enables the asynchronous timeout interrupt. Writing a 1 to
this bit sets this bit and the ATMCLR bit in the EMIF interrupt mask clear register (EIMCR), and enables
the asynchronous timeout interrupt. To clear this bit, a 1 must be written to the ATMCLR bit in EIMCR.
0 Indicates that the asynchronous timeout interrupt is disabled. Writing a 0 has no effect.
1 Indicates that the asynchronous timeout interrupt is enabled. Writing a 1 sets this bit and the ATMCLR
bit in EIMCR.
57
SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF)
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