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Registers
Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions (continued)
Bit Field Value Description
0 ATM Asynchronous Timeout Masked. This bit is set to 1 by hardware to indicate that during an extended
asynchronous memory access cycle the EM_WAITn pin did not go inactive within the number of cycles
defined by the MEWC field in the asynchronous wait cycle configuration register (AWCCR), provided
that the ATMSET bit is set to 1 in the EMIF interrupt mask set register (EIMSR).
0 Indicates that an asynchronous timeout interrupt has not been generated. Writing a 0 has no effect.
1 Indicates that an asynchronous timeout interrupt has been generated. Writing a 1 will clear this bit and
the AT bit in the EMIF interrupt raw register (EIRR).
55
SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF)
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