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3.1.4 Example Using TC5516100FT-12
This section takes you through the configuration steps required to implement Toshiba’s TC55V1664FT-12
ASRAM with the EMIF. The following assumptions are made:
• ASRAM is connected to chip select space 3 (EM_CS[3])
• EMIF clock speed is 100 MHZ (t
cyc
= 10 nS)
Table 20 lists the data sheet specifications for the EMIF and Table 21 lists the data sheet specifications
for the ASRAM.
Table 20. EMIF Timing Requirements for TC5516100FT-12 Example
Parameter Description Min Max Units
t
SU
Data Setup time, data valid before EM_OE high 5 nS
t
H
Data Hold time, data valid after EM_OE high 0 nS
Table 21. ASRAM Timing Requirements for TC5516100FT-12 Example
Parameter Description Min Max Units
t
ACC
Address Access time 12 nS
t
OH
Output data Hold time for address change 3 nS
t
RC
Read cycle time 12 nS
t
WP
Write Pulse width 8 nS
t
AW
Address valid to end of Write 9 nS
t
DS
Data Setup time 7 nS
t
WR
Write Recovery time 0 nS
t
DH
Data Hold time 0 nS
t
WC
Write Cycle time 12 nS
t
COD
Output Disable time from chip enable 7
Table 22 lists the values of the PCB board delays. The delays were estimated using the rule that there is
180 pS of delay for every 1 inch of trace.
Table 22. Measured PCB Delays for TC5516100FT-12 Example
Parameter Description Delay (ns)
Read Access
t
EM_CS
Delay on EM_CS from EMIF to ASRAM. EM_CS is driven by EMIF. 0.36
t
EM_A
Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF. 0.27
t
EM_OE
Delay on EM_OE from EMIF to ASRAM. EM_OE is driven by EMIF. 0.36
t
EM_D
Delay on EM_D from ASRAM to EMIF. EM_D is driven by ASRAM. 0.45
Write Access
t
EM_CS
Delay on EM_CS from EMIF to ASRAM. EM_CS is driven by EMIF. 0.36
t
EM_A
Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF. 0.27
t
EM_WE
Delay on EM_WE from EMIF to ASRAM. EM_WE is driven by EMIF. 0.36
t
EM_D
Delay on EM_D from EMIF to ASRAM. EM_D is driven by EMIF. 0.45
37
SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF)
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