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Adapter Host Registers
A-14
Table A–5. Host
_
CMD Register Bits (Continued)
Bit FunctionName
29 Ack Interrupt acknowledge: Writing a 1 to this bit acknowledges the interrupt indicated by
the Nes, EOC, Ch_Sel, and R/T fields.
if Nes = 0, EOC = 1, and R/T = 1 (Status Ack):
Writing a 1 to this bit acknowledges and clears the status interrupt.
if Nes = 0, EOC = 0, and R/T = 1 (Statistics Ack):
Writing a 1 to this bit acknowledges and clears the statistics interrupt.
if Nes = 1, EOC = 1, and R/T = 0 (Tx EOC Ack):
Writing a 1 to this bit acknowledges and clears a Tx EOC interrupt for the channel indi-
cated in Ch_Sel.
if Nes = 1, EOC = 1, and R/T = 1 (Rx EOC Ack):
Writing a 1 to this bit acknowledges and clears a Rx EOC interrupt for the channel indi-
cated in Ch_Sel.
if Nes = 1, EOC = 0, and R/T = 0 (Tx EOF Ack):
Writing a 1 to this bit acknowledges and clears 1 or more Tx EOF interrupts for the chan-
nel indicated in Ch_Sel, as indicated in the Ack Count field. If an attempt is made to ac-
knowledge more EOFs than the adapter has outstanding, an AckErr adapter check is
raised.
if Nes = 1, EOC = 0, and R/T = 1 (Rx EOF Ack):
Writing a 1 to this bit acknowledges and clears 1 or more Rx EOF interrupts for the chan-
nel indicated in Ch_Sel, as indicated in the Ack Count field. If an attempt is made to ac-
knowledge more EOFs than the adapter has outstanding, an AckErr adapter check is
raised.
Because of the internal calculations required in Tx EOF and Rx EOF acknowledges,
the HOST_INT
register is not updated immediately. A short delay (six PCI cycles) is re-
quired before reading HOST_INT for such acknowledges to take effect.
Writing a 0 to this bit has no effect. This bit is always read as 0.
28–21 Ch_Sel Channel select: This read/write field is used to select between channels on a multi-
channel adapter. This 8-bit field encodes the channel number (0 through 255). As this
adapter supports two channels, only the LSBs are implemented. All the MSBs (28
through 22) are hardwired to 0. This field is written in the same cycle as the command
bits and allows a command to be issued in a single write cycle.