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MII PHY Registers
2-20
Interrupts are turned off with the CritOn() macro. This macro leaves a value
that can be sampled to see if it has been invoked. CritOn can be defined as
follows:
#define CritOn() if (CritLevel == 0) \
{ _asm { cli } } \
CritLevel++
The NetSio register must be reached indirectly using the host registers. This
sets the address of the NetSio register, offset from the beginning of the internal
register block, in the host register which is used as an address pointer to the
Internal registers. This is a two-active-byte-strobe (out of four) write cycle. The
DIO_ADR register is 16 bits in width.
b = inp(diodata);
b &= ~MINTEN;
b &= ~MDATA;
b |= MCLK;
outp(diodata,b);
This cycle reads, modifies, and writes the contents of the NetSio register. It
turns off the MII interrupt by forcing the MINTEN bit to a logic low, makes sure
the data bit in the interface comes on with a logic low when enabled in the next
write, and makes sure the clock line in the two-wire MII management interface
starts high.
b |= MTXEN;
outp(diodata,b);
The previous code turns on the data output driver. ThunderLAN has to write
several fields to the MII before data is passed in either direction.
//togLH
b &= ~MCLK; outp(diodata,b);
b |= MCLK; outp(diodata,b); //0 data bit out