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Adapter Host Registers
A-18
A.2.3 Host Interrupt Register–HOST_INT @ Base_Address + 10 (Host)
00
Int TypeInt Vec
000
0123456789101112131415
Table A–6.
HOST_INT Register Bits
Bit Name Function
15–13 0 These bits are always read as 0s.
12–5 Int_Vec Interrupt vector: This field indicates the highest active interrupt flag for a particular inter-
rupt type. Its format depends on the value read in the Int_type bit. This field is read only.
4–2 Int_Type Interrupt type: This field indicates the type of interrupt, and therefore, the format of the
Int_Vec field. The three bits are coded as follows:
000: No interrupt (invalid code)
001: Tx EOF
010: Statistics overflow
011: Rx EOF
100: Dummy interrupt (created by Req_Int command bit)
101: Tx EOC
110: Adapter check/network status
If Int_Vec is 0, this is a network status interrupt.
If Int_Vec is not 0, this is an adapter-check interrupt.
111: Rx EOC
This field is read only, but writing a nonzero value to it causes the adapter PCI interrupt
to be disabled (deasserted) until after a 1 is written to the Ack command bit (in
HOST_CMD).
If this register is not written to, it maintains the highest priority interrupt that is available,
even if the driver is currently servicing a lower priority interrupt.
1 0 This bit is always read as 0.
0
0 This bit is always read as 0.
The HOST_ INT register indicates the reason for a ThunderLAN PCI interrupt.
The bit positions in this register are arranged so that its contents may be used
as a table offset in a jump table to allow a quick jump to the appropriate interrupt
service routine.
The 16 MSB positions in the HOST_CMD register have a one-for-one corre-
spondence with those in the HOST_INT register. The Int_Vec field corre-
sponds to the Ch_Sel field, and the Int_type field corresponds to the EOC, R/T,