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Adapter Internal Registers
A-27
Register Definitions
A.3.5 Network Configuration Register–NetConfig @ 0x04 (DIO)
This 16-bit register is used for ThunderLAN’s controller configuration. This
register is only writable while the ThunderLAN controller is in reset. (NRESET
= 0). All bits in this register are set to 0 on an Ad_Rst or when PRST# is as-
serted.
Byte 0Byte 1
MAC select
En
PHY
test
Man
chn
One
fragment
One
PEF
CRC
Rx
rate
BIT
test
Tclk
test
Rclk
0123456789101112131415
Table A–12. Network Configuration Register Bits
Bit Name Function
15 Rclk test Test MRCLK: This test/sense bit allows the host to verify the presence of a clock on the
MRCLK pin. This bit can only be written as a 1. Writing a 0 to this bit has no effect. This
bit is cleared to 0 by a rising edge on MRCLK. Host software verifies a minimum clock
frequency by setting this bit, waiting for the maximum clock period, and then verifying
the bit has been cleared.
14 Tclk test Test MTCLK: This test/sense bit allows the host to verify presence of a clock on the
MTCLK pin. This bit can only be written as a 1. Writing a 0 to this bit has no effect. This
bit is cleared to 0 by a rising edge on MTCLK. Host software verifies a minimum clock
frequency by setting this bit, waiting for the maximum clock period, and then verifying
the bit has been cleared.
13
BITrate Bit rate MII: When this bit is set to 1, ThunderLAN supports a bit-level (rather than nibble-
level) CSMA/CD MII. This mode is only valid for 10M-bps operation. The MII pins can
be tied to a standard Ethernet SNI that follows the NS8391 interface. In this mode, the
MII pins should be connected as follows:
MRXD0 to RXD (receive data)
MRCLK to RXC (receive clock)
MCRS to CRS (carrier sense)
MTCLK to TXC (transmit clock)
MTXD0 to TXD (transmit data)
MTXEN to TXE (transmit enable)
MCOL to COL (collision detect)
MTXD3, MTXD2, MTXD1, and MTXER are driven with values contained in the low
nibble (bits 0–3) of the Acommit register. These signals can be used to drive PHY
option pins, such as loopback or UTP/AUI select.