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MII PHY Registers
2-24
{
for (i = 0;i < 17;i++)
togLH(MCLK);
tmp = 0xffff;
}
//togLH
b &= ~MCLK; outp(diodata,b);
b |= MCLK; outp(diodata,b);
b = inp(diodata);
This is the quiescent cycle following data transmission. Since this is a read op-
eration, ThunderLAN does not drive the line and the PHY turns off during this
cycle. If the quiescent cycle is not performed between the read and write op-
erations, the PHY is not able to assert the MDIO pin low to indicate a PHY inter-
rupt. After this cycle and a read, the driver sets the MINTEN bit high, which en-
ables PHY interrupts.
set(MINTEN);
*pval = tmp;
CritOff();
The function value returned is reserved for completion and error codes, and
is returned via a pointer. CritOff turns on the interrupts again and is defined as:
#define CritOff() if (––CritLevel == 0) \
{ _asm { sti } }
A similar routine with similar code is used to write values into the PHY registers
through the management interface.