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PCI Configuration Registers
A-2
A.1 PCI Configuration Registers
The PCI specification requires all PCI devices to support a configuration regis-
ter space to allow jumperless autoconfiguration. The configuration space is
256 bytes in length, of which the first 64-byte header region is explicitly defined
by the PCI standard. Registers in this address space are accessed by a com-
bination of signals. The IDSEL pin acts as a classical chip-select signal, indi-
cating there are configuration accesses to this device. Special configuration
read or write cycles are used for the accesses and individual registers are ad-
dressed using AD[7::2] and PCI bus-byte enables.
The adapter only implements mandatory or applicable configuration registers
in the standard PCI header region. No adapter-specific configuration registers
are defined. The adapter’s PCI configuration register address map is shown
in the diagram below. All reserved registers are read as 0. The registers shown
shaded in the diagram can be autoloaded from an external serial EEPROM.