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TNETE211 Register Descriptions
B-8
Table B–1. PHY Generic Control Register Bits (Continued)
Bit Name Function
11 PDOWN Power down: When this bit is set (default), the PHY is placed in a low-power consump-
tion state. This bit resets the 802.12 MAC state machine to MAC0. It stops the Tx and
Rx functions and disables the oscillator by deasserting POSCEN
†
. In power-down
mode, PDOWN is the only bit that can be written to.
10 ISOLATE Isolate: When this bit is set (default), the PHY electrically isolates its data paths from the
MII. In this state it does not respond to MTKD[3::0], MTXEN, and MTXER inputs, and
presents a high impedance on its MTCLK, MRCLK, MRXDV, MRXER, MRXD0–3, and
MCOL outputs. It will, however, still respond to management frames on MDIO and
MDCLK.
9 0 Autoconfiguration
enable: Not implemented
8 0 Duplex mode: VG currently does not support a full-duplex mode
7 COLTEST Collision test mode: Setting this bit to 1 causes the PHY to assert the collision sense
signal MCOL whenever transmit enable (MTXEN) is asserted.
6–0
Reserved Read as 0
†
Oscillator enable from the TNETE211
B.2.2 PHY Generic Status Register –GEN_sts @ 0x1
1JABBERLINK0RFLT00000
Byte 0Byte 1
Reserved
0123456789101112131415
0
Table B–2. PHY Generic Status Register Bits
Bit Name Function
15 0 100Base-T4 capable: Not supported
14 0 100Base-Tx full-duplex capable: Not supported
13 0 100Base-Tx half-duplex capable: Not supported
12 0 10Base-T full-duplex capable: Not supported
11 0 10Base-T half-duplex capable: Not supported
10–6 Reserved Read as 0
5
0 Autoconfiguration complete: Not implemented