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MII PHY Registers
2-19
ThunderLAN Registers
After synchronization, one could use code like the following to read a PHY reg-
ister:
//––––––––––––––––––––––––––––––––––––––––––––––––––––––––
// MiiRdWord() – Read word from Phy MII, place at ptr,
return status
//
// Parameters:
// base_addr WORD base address of TLAN internal regis-
ters (passed
// for set/clr macros)
// dev WORD device to read from
// addr WORD register on dev to read from
// pval WORD* storage for data read
//
// Return val:
// int OK (0) on success, NO_ACK (1) on failure
//––––––––––––––––––––––––––––––––––––––––––––––––––––––––
int MiiRdWord(WORD base_addr, WORD dev, WORD addr, WORD
*pval)
{
// mread array: 01 is the start delimiter sequence for
the MII
// interface, 10 specifies the operation will be a
read.
// See IEEE 802.3u
WORD i,tmp;
char ack;
BYTE b;
WORD diodata = base_addr+OFF_DIO_DATA+Net_Sio;
CritOn();
outpw(base_addr+OFF_DIO_ADDR,Net_Sio);
This example uses the host registers as I/O ports, so the code needs to resolve
a pointer to the host NetSio register. NetSio is added to the base DIO_DATA
register address to give the byte offset. The NetSio register is only one byte
long, and a byte port read instruction needs to activate the proper byte strobe
in the PCI interface. Filling in the lowest two bits with the NetSio offset constant
causes the NetCmd register to be read.